Q1: Based on the code bellow, answer the following questions: (answer 3 of the following) A- By the end of the execution, the value of RO........, R1 =..........., R2 =............. and the conditional branch will be taken.............. times? B- Given the single cycle architecture bellow find the control signals of the following assembly code. C- Draw the required adjustments to architecture bellow to make it a multi-cycle architecture.

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Q1: Based on the code bellow, answer the following questions: (answer 3 of the following)
A- By the end of the execution, the value of RO..........1........................... and the conditional
branch will be taken.............times?
B- Given the single cycle architecture bellow find the control signals of the following assembly code.
C- Draw the required adjustments to architecture bellow to make it a multi-cycle architecture.
D- Assume the code bellow is running on pipeline architecture with no forwarding or hazard detection,
insert NOPs and rearrange if possible to ensure correct execution then draw the timeline of pipeline
diagram.
Label Code
00
01
03
04
05
06
07
08
LDR R1, #2008
MOV RO, #0
LSR R1, R1, #1
ADD RO, #2
CMP R1, #0
BEQ #03
End
0x1B
AL [2:0]
000
Function
not In
II and I₁
| In xor I
In or I
001
010
0 1 1
100 | In - 1
101 | In + In
110
111
1 In - I₁
II + 1
SHIN:0]
OO #VAL |
Function
Shift << VAL
Rotate << VAL
Shift >> VAL
0 1 #VAL |
1 0 #VALI
1 1 #VAL | Rotate >> VAL
RA
R.B
WEN
WA
IMM.
SHIFTER
SH
FLAGS
DATA MEMORY
IN
OUT
OEN
MDA
$310
MA
ROR1 R2 R3 R4 R5 R6 R7
CK
54
Transcribed Image Text:Q1: Based on the code bellow, answer the following questions: (answer 3 of the following) A- By the end of the execution, the value of RO..........1........................... and the conditional branch will be taken.............times? B- Given the single cycle architecture bellow find the control signals of the following assembly code. C- Draw the required adjustments to architecture bellow to make it a multi-cycle architecture. D- Assume the code bellow is running on pipeline architecture with no forwarding or hazard detection, insert NOPs and rearrange if possible to ensure correct execution then draw the timeline of pipeline diagram. Label Code 00 01 03 04 05 06 07 08 LDR R1, #2008 MOV RO, #0 LSR R1, R1, #1 ADD RO, #2 CMP R1, #0 BEQ #03 End 0x1B AL [2:0] 000 Function not In II and I₁ | In xor I In or I 001 010 0 1 1 100 | In - 1 101 | In + In 110 111 1 In - I₁ II + 1 SHIN:0] OO #VAL | Function Shift << VAL Rotate << VAL Shift >> VAL 0 1 #VAL | 1 0 #VALI 1 1 #VAL | Rotate >> VAL RA R.B WEN WA IMM. SHIFTER SH FLAGS DATA MEMORY IN OUT OEN MDA $310 MA ROR1 R2 R3 R4 R5 R6 R7 CK 54
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