Database System Concepts
7th Edition
ISBN: 9780078022159
Author: Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher: McGraw-Hill Education
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Concept explainers
Question
make the test bench(instantiation) and explain how the test bench works (Verilog)
![1 module Examenler
2 #(parameter P = 4)
HN3Ahor∞a
777
4日(
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AWNI
HANNNNNNNNN M M M M
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~34567∞aOHNM
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-0
-0-0
П
input [P:0] e_a,
input [P:0] e_b,
output reg [P+1:0] vs_a
always @*
begin
if (e_a[P]
begin
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31
32
33 endmodule
= e_b[P])
vs_a[P:0] = e_a[P-1:0] + e_b[P-1:0];
_vs_a [P+1] = e_a[P];
end
else
end
begin
if
(e_a[P-1:0] > e_b[P-1:0])
begin
vs_a[P:0] = e_a[P-1:0] - e_b[P-1:0];
vs_a[P+1] e_a[P];
=
end
else
end
begin
vs_a[P:0]
vs_a[P+1]
end
= e_b[P-1:0]
e_b[P];
=
vs_a [P-1:0];](https://content.bartleby.com/qna-images/question/f5b3d930-7552-4451-a258-e7043430e51e/1f61dd0e-6d3e-4650-85f4-3ea8a8c63a3d/1x8xljn_processed.png)
Transcribed Image Text:1 module Examenler
2 #(parameter P = 4)
HN3Ahor∞a
777
4日(
5
6
7
8
9
10
11
12
13
14
15
16
17
18
AWNI
HANNNNNNNNN M M M M
19
20
21
~34567∞aOHNM
22
23
24
25
26
27
28
29
-0
-0-0
П
input [P:0] e_a,
input [P:0] e_b,
output reg [P+1:0] vs_a
always @*
begin
if (e_a[P]
begin
30
31
32
33 endmodule
= e_b[P])
vs_a[P:0] = e_a[P-1:0] + e_b[P-1:0];
_vs_a [P+1] = e_a[P];
end
else
end
begin
if
(e_a[P-1:0] > e_b[P-1:0])
begin
vs_a[P:0] = e_a[P-1:0] - e_b[P-1:0];
vs_a[P+1] e_a[P];
=
end
else
end
begin
vs_a[P:0]
vs_a[P+1]
end
= e_b[P-1:0]
e_b[P];
=
vs_a [P-1:0];
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