In a digital communication, explain all the methods/mechanism used for the minimization of Bit Error Rate (BER). Also state that which method/mechanism is preferred and why?

4 O T O 1.3 Design a combinational logic circuit for full-adder using only NAND gates. Filters Add a caption.

None

Draw the implementation of decoding of binary state 5, and binary state 3 for a 3- bit synchronous binary counter. Show the entire timing diagram and the output waveforms of the decoding gates.

4

communication sys

UTMO-bit binary number UIMO1010, determine the equivalent binary Q.1 Answer the following questions. Clearly show your work. (a) Given a hexadecimal number 87FE, convert to its equivalent number in binary. How many bytes are required to represent the number? 5 UTM & UTM" (b) Given an representation in unsigned decimal (i.e. standard binary). If the binary number UTM & UTM 8 UTM TUT above is represented in sign-magnitude, determine its equivalent representation in 2's complement. (c) Assume that you have two numbers A and B that are represented in 4-bit 2's UTM 3 UTM 5 UTM TM UTM & UTM 5 UTM 5 UTS (d) UTM 5 UTM 5 UTM UTM 5 UTM 3 TITM 5 UT F(x,y,z) = xz + z(x+ xy) 5 UTM TM & UTM TM 8 UTM 5 UTM 5 UT 5 UTM F(A,B,C) = AB + BC 5 UTM 5 UTM 5 UTM 5 UTM 5' 5 UTM 5 UTM 5 UTM UT

(a) Write an 8086 program for our LAB emulator that sort descendingly the followng sequence : 1, 212, 423, ... , 10129. program should be general, free from syntax or logical errors, and if in error result will be cancelled. (b) Write the fifth term in hex after sort.

Write the truth table of 3 to 8 line decoder and derive the Boolean expression and finally draw the logic level circuit diagram of 3 to 8 line decode. (you can use AND or NAND gate)

Implementation of 8-bit Floating Light Digital Circuit Using JK Flip-Flopdesign it. (Hint: Using Shift Register)