I have a 24 MHz fast 8051 microcontroller, by ATMEL. It has a machine cycle of 12 clocks. I would like to generate a time delay of 512 microseconds (µs = 10-6). Design your timer without using mode 1. 1. Which Timer and what mode are you going to use? 2. What is the delay count and the base number of your design? 3. Configure and program the TMOD register according to your design.  4. Write the assembly code of your design to program the microcontroller and generate the 512 µs delay!

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I have a 24 MHz fast 8051 microcontroller, by ATMEL. It has a machine cycle of 12 clocks. I
would like to generate a time delay of 512 microseconds (µs = 10-6). Design your timer
without using mode 1.
1. Which Timer and what mode are you going to use?
2. What is the delay count and the base number of your design?
3. Configure and program the TMOD register according to your design. 
4. Write the assembly code of your design to program the microcontroller and generate
the 512 µs delay!

BIT
IP.7
IP.0
IP.5
IP.4
IP.3
IP.2
IP.1
IP.0
BIT
IE.7
mmmmmm
IE.8
IE.5
IE.4
IE.3
IE.2
IE.1
IE.O
PS
PT1
PX1
MSB
SYMBOL FUNCTION
Reserved.
PTO
PXD
x
-
8051 REFERRENCE MANUAL
ES
ET1
EX1
ΕΤΟ
EXO
SYMBOL
EA
Reserved.
Reserved.
Defines the Serial Port interrupt priority level. PS-1 programs it to the higher priority level.
Defines the Timer 1 interrupt priority level. PT1=1 programs it to the higher priority level.
Defines the External Interrupt 1 priority level. PX1=1 programs it to the higher priority level.
Enables or disables the Timer O interrupt priority level. PTO-1 programs it to the higher priority level.
Defines the External Interrupt 0 priority level. PX0=1 programs it to the higher priority level.
MSB
PS PT1
EA
LSB
PX1 PTO PXO
RESET values of IP and IE = 0000 0000B
Figure 19. Interrupt Priority Register (IP)
x ES ET1 EX1 ETO
LSB
EXO
FUNCTION
Disables all interrupts. If EA=0, no interrupt will be acknowledged. If EA=1, each interrupt
source is individually enabled or disabled by setting or clearing its enable bit.
Reserved.
OUCOSAS
Reserved.
Enables or disables the Serial Port interrupt. If ES=0, the Serial Port interrupt is disabled.
Enables or disables the Timer 1 Overflow interrupt. If ET1=0, the Timer 1 interrupt is disabled.
Enables or disables External Interrupt 1. If EX1-0, External interrupt 1 is disabled.
Enables or disables the Timer 0 Overflow interrupt. If ETO=0, the Timer O interrupt is disabled.
Enables or disables External interrupt 0. If EXD=0, External interrupt 0 is disabled.
Figure 18. Interrupt Enable Register (IE)
BUD0544
Transcribed Image Text:BIT IP.7 IP.0 IP.5 IP.4 IP.3 IP.2 IP.1 IP.0 BIT IE.7 mmmmmm IE.8 IE.5 IE.4 IE.3 IE.2 IE.1 IE.O PS PT1 PX1 MSB SYMBOL FUNCTION Reserved. PTO PXD x - 8051 REFERRENCE MANUAL ES ET1 EX1 ΕΤΟ EXO SYMBOL EA Reserved. Reserved. Defines the Serial Port interrupt priority level. PS-1 programs it to the higher priority level. Defines the Timer 1 interrupt priority level. PT1=1 programs it to the higher priority level. Defines the External Interrupt 1 priority level. PX1=1 programs it to the higher priority level. Enables or disables the Timer O interrupt priority level. PTO-1 programs it to the higher priority level. Defines the External Interrupt 0 priority level. PX0=1 programs it to the higher priority level. MSB PS PT1 EA LSB PX1 PTO PXO RESET values of IP and IE = 0000 0000B Figure 19. Interrupt Priority Register (IP) x ES ET1 EX1 ETO LSB EXO FUNCTION Disables all interrupts. If EA=0, no interrupt will be acknowledged. If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit. Reserved. OUCOSAS Reserved. Enables or disables the Serial Port interrupt. If ES=0, the Serial Port interrupt is disabled. Enables or disables the Timer 1 Overflow interrupt. If ET1=0, the Timer 1 interrupt is disabled. Enables or disables External Interrupt 1. If EX1-0, External interrupt 1 is disabled. Enables or disables the Timer 0 Overflow interrupt. If ETO=0, the Timer O interrupt is disabled. Enables or disables External interrupt 0. If EXD=0, External interrupt 0 is disabled. Figure 18. Interrupt Enable Register (IE) BUD0544
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