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- Write the assembly code c=a-b for the calculation in MIPSDraft a VHDL model for an ALU that considers RV32i instructions.Convert the following a sequential circuit in pipelined design Calculate the throughput (T) and latency (L) What is the bottleneck block in the given design? Explain circuit interleaving and apply it into the given circuit for solving the bottleneck issue.
- Convert the following a sequential circuit in pipelined design b- Calculate the throughput (T) and latency (L) What is the bottleneck block in the given design? d- Explain circuit interleaving and apply it to the given circuit for solving the bottleneck issue. X. A B. 3ns 4ns 8ns Y. D 4ns C 2ns 4nsTask: Modify the Laser Circuit FSM to output x for 25 ns, assuming Tclk = 5 ns. Given VHDL code for the Laser Circuit FSM: library ieee;use ieee.std_logic_1164.all; entity LaserTimer isport ( b: in std_logic;x : out std_logic;clk, rst : in std_logic;);end LaserTimer; architecture behavior of LaserTimer istype statetype is(S_Off, S_On1, S_On2, S_On3);signal currentState, nextState:statetype; beginstatereg: process(clk, rst)beginif (rst=’1’) thencurrentstate <= S_Off;elsif (clk=’1’ and clk’event) thencurrentstate <= nextstate;end if;end process; comblogic: process (currentstate, b)begincase currentstate iswhen S_Off =>x <= ‘0’;if (b=’0’) thennextstate <= S_Off;elsenextstate <= S_On1;end if;when S_On1 =>x <= ‘1’;nextstate <= S_On2;when S_On2 =>x <= ‘1’;nextstate <= S_On3;when S_On3 =>x <= ‘1’;nextstate <= S_Off;end case;end process;end behavior;You are designing an IEEE single-precision floating-point multiplier targeting 200 MHz operation in a 0.18-micron process using synthesized static CMOS logic and conventional flip-flops. The flip-flops in your cell library have a setup time of 200 ps and a clock-to-Q delay of 300 ps for the expected loading. You are budgeting clock skew of 400 ps. How much time (in nanoseconds) is available for useful multiplier logic?
- The frequency of the crystal oscillator for 80C51 MCU is 12MHz. Design a software delay program with a delay time of 20ms in assembly language.Design an interfacing circuit to interface a 2KB ROM and 4KB RAM to 8085 processor.Construct the circuit diagram for this 4-bit Parallel Adder source code: Run this program in verilog: module main(in1,in2,ic,out,oc);input [3:0]in1;input [3:0]in2;input ic;output [3:0]out;output [3:0]oc;fulladder fa1(in1[0],in2[0],ic,out[0],oc[0]);fulladder fa2(in1[1],in2[1],oc[0],out[1],oc[1]);fulladder fa3(in1[2],in2[2],oc[1],out[2],oc[2]);fulladder fa4(in1[3],in2[3],oc[2],out[3],oc[3]);endmodule.
- Write an 8051 assembly program to use Counter 1 in mode 2 and after 10 number of counts on TL1, generate a SQUARE waveform of 1 KHz on P1.2 by using Timer 1 in mode 1, show the counts in TL1 on port 2. Execute the program in Keil simulatorGiven the following Combinational circuit, Use Verilog HDL on Quartus tool to1. Write a Verilog HDL code to describe the module DCDR2×4 // this module name must be your last name ( younis2. Write a Verilog HDL code to describe the whole system structurally from its subsystems// this module name must be your university number ( 1181230)Give at least two examples of synchronous function and asynchronous function of RPC. List at least four disadvantages of RPC.