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Give an example where higher set associativity really raises miss rate in the miss rate table. To show this, build a cache setup and a reference stream.
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- "Spatial locality" and "temporal locality" boost performance with caches. These two events benefit caches.For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache.Tag Index Offset31–10 9–5 4–01. What is the cache block size (in words)?2. How many entries does the cache have?3. What is the ratio between total bits required for such a cache implementation over the data storage bits?Starting from power on, the following byte-addressed cache references are recorded. Address 0 4 16 132 232 160 1024 30 140 3100 180 2180 How many blocks are replaced? What is the hit ratio? List the fi nal state of the cache, with each valid entry represented as a record of <index, tag, data>Develop a C/C++ program that accepts the name of a memory trace file as a command line argument. Use the data to simulate a set associative cache using LRU replacement. Additional command line arguments will be needed to identify the details of the simulated cache. The arguments should appear in the following order: the memory trace input file X, where 2X == the number of direct-mapped sets Y, where 2Y == the number of blocks per set Z, where 2Z == the number of cached words per block Your program (say it's a compiled C program) could be run like this: ./cache data.tra 3 2 4 This would simulate an 8 set associative LRU cache with 4 blocks per set, where each block caches 16 addresses. NOTE… the reason I've chosen to use exponents for arguments is to ensure we have powers of 2 for everything. Trace File The trace file is line based with each line containing a memory address requested, in hex. Please note this data is real, so the addresses are larger than 32-bits. In…
- Conflict Based on what we've learned about caches in this class, which of the following situations will cause two blocks to conflict? a) diff tag diff set, diff offset b) diff tag, diff set, same.offset c) diff tag same set, diff offset d) diff tag same set, same offset e) same tag diff set diff offset) f) same tag, diff set, same offset g) same tag, same set, diff offset h) same tag, same set, same offset please I need correct answers in 45 minutes I will give upvote“Prefetching” is a technique that leverages predictable address patterns to speculatively bring in additional cache blocks when a particular cache block is accessed. One example of prefetching is a stream buff er that prefetches sequentially adjacent cache blocks into a separate buff er when a particular cache block is brought in. If the data is found in the prefetch buff er, it is considered as a hit and moved into the cache and the next cache block is prefetched. Assume a two-entry stream buff er and assume that the cache latency is such that a cache block can be loaded before the computation on the previous cache block is completed. What is the miss rate for the address stream above?Cache block size (B) can aff ect both miss rate and miss latency. Assuming a 1-CPI machine with an average of 1.35 references (both instruction and data) per instruction, help find the optimal block size given the following miss rates for various block sizes. 8: 4% 16: 3% 32: 2% 64: 1.5% 128: 1%…Is there a way to find out which parts of a log entry a certain log processing function can read? The following code determines the typical number of cache misses per entry while using 64-byte cache blocks and no prefetching.
- Make the difference between a cache that is directly mapped and one that is totally associative.Different algorithms are used for scheduling the disk head so that seek time may be reduced. Calculate total number of heads movement for the following algorithms for the given disk queue with requests for I/O to blocks on cylinders in that order. Queue = 98, 183, 37, 122, 14, 124, 65, 67 If the disk head is initially at cylinder 53 and direction is Right. FCFS – First-Come, First-Served - FCFSGive an example in the miss rate table where higher set associativity actually increases miss rate. Construct a cache configuration and reference stream to demonstrate this.
- Consider a fully-associative cache of size 4. Each slot in the cache can have just one item (i.e. the line size is 1 item). The cache is empty to start with. The cache uses an LRU replacement policy: every slot has a counter; every time a slot is accessed, a global counter is incremented and the value is stored in the slot counter; the slot with the lowest counter value is chosen for replacement. Sequence Id 1 2 3 4 5 6 7 8 10 Address Ox0012 0x0014 Ox0016 Ox0018 0x0016 0x0012 0x0020 Ox0022 0x0014 Ox0012 Hit/Miss Accesses 1 to 10 are respectively: Select one: O a. Miss, Miss, Miss, Miss, Hit, Hit, Miss, Miss, Miss, Miss O b. Miss, Miss, Miss, Miss, Hit, Hit, Miss, Miss, Hit, Hit O. Miss, Miss, Miss, Miss, Hit, Hit, Miss, Miss, Hit, Miss O d. Miss, Miss, Miss, Miss, Hit, Miss, Miss, Miss, Miss, Hit O e. Miss, Miss, Miss, Miss, Hit, Hit, Miss, Miss, Miss, HitCA_7 Let a program use 5 contiguous words and loop these words 100 times (meaning the execution trace of this program is [012340123401234...1. Furthermore, let a cache have 4 word-sized blocks. How many misses will there be if the cache is: (a)Direct mapped? (b) Fully-associative with commonly used Least-Recently-Used replacement? (c) Fully-associative with less well-known Most-Recently-Used replacement? (d) Set-associative with two sets and uses first-in-first-out replacement? (e) Set-associative with two sets and uses first-in-last-out replacement?The paging problem arises from the limitation of finite space. Let's assume our cache C has k pages. Now we want to process a sequence of m page requests which must have been placed in the cache before they are processed. Of course if m<=k then we just put all elements in the cache and it will work, but usually is m>>k. There are two ways to approach this problem:offline and online solve using both approach