f(x, y, z) = Zx + zy + xy; implement the given function by; →2x1 MUX and if required NAND gate(s) →4x1 MUX and if required NOR gate(s) 3x8 Decoder and if required NAND gate(s) 2
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- Construct a circuit diagram that checks whether the two numbers A and B are in the ratio of 2:3. Also, derive the final Boolean equation for the function. F = 1 if A: B = 2: 3,0 otherwise Here, A and B both are 3 bit binary numbers. NB: You cannot use the IC of comparator, meaning for the comparison part, you need to draw the gate level diagram. You can use block level diagrams for the rest of the parts.DISCUSSION: 1- Design the logic eircuit for the following conditions and draw the output wave form, X is a 0 if any two of the three variables A, B, and C are 1, X is al for all other conditions. 2- Implement the following function with only AND and NOT gates, F-AB+AB+BC W-XY (XZ+XY Z+ Y Z) + XZ 3- Use NAND gate, NOR gate, or combinations of both to implement the following expression:- a) X-A [B + C (D +E)] b) X B (CDE+EF G) (A B+ C) 4-a) What is the applications of AND gate and OR gate? b) In OR gate why 1 +1 1? c) The Fig. (1-12 ) shows the A & B inputs and the output is C, For the OR gate using the A and B inputs of Fig. (1-12) draw the C output for each of the following: The AND gate. • The NAND gate. • The NOR gate. .The EX-OR gate. • The EX-NOR gate. 1-12A- Figure 1 shows a 2-input TTL NAND gate. 1). Discuss in details the operation of the NAND circuit 2). Is this circuit saturated logic circuits non-saturated logic? 3). Discuss in bravely the function of DI. +Vec =5V R1 4 kN 13多0 iz R2 1.6 k2 R3 130 2 VB1 Output V82 igo Co R4 1.0 K Figure 1
- 4. Design a circuit that has 'n' bit binary code output with '2n' input lines.7. A certain TTL. gate has lat -20 A, la 01 mA, kan 04 mA and ke4 mA. Determine the input and ourput loading in the HIGH and LOw states in terms of UL. When the I UL (LOW state)-1.6 mA and I UL (HIGH state)40 A.i) Solve Vo for each of the circuits shown below. Assume that Vtn = |Vtpl = 0.5V, that there is no subthreshold cond oV 2.5V OV 2.5V Vo 2.5V. 2.5V %3D Construct the function F = ac'd'+acd+a'cb´+a'c'b using PMOS Pass Transistor Logic
- Using a K-Map, simplify the logic function F and construct the circuit using only NAND gates. F(x, y, z) = xz + xyz + yzDesign an Exclusive OR (XOR) logic gate using only the CMOS inverter, NAND, or NOR gates you learned in the class. (Hint: you may need to review the De Morgan's Law you learned in your digital logic courses). Draw the transistor level circuit diagram of the XOR gate. Input Input AB Output 00 0 0 1 1 10 1 1 1 0 Output = A + B = AB + ABIn this problem we'll explore the fact that all logical circuits can be implemented using just NAND gates. The figure below shows you the symbol for a NAND gate and its truth table. We then show you how NAND gates can be wired together to perform the equivalent of a NOT gate, an AND gate, and an OR gate. NAND gate AB Output 1 01 1 Inputa Inputg Output 10 1 11 NOT A- AND D B. A. OR B. 2 i. Let's denote p NAND q as pīq. Write a logical expression for the thrce circuits corresponding to AND, OR, and NOT. ii. Validate your three logical expressions with three truth tables. For clarity and full credit, show cach variable and distinct sub-clause in a separate column, culminating in your final formula. 3. 2.
- Design a combinational circuit with 3 inputs and 1 output. The output must be logic 1 when the binary value of the inputs have more 1’s than 0’s and logic 0 otherwise. Use only NAND Gates. (show All the steps)For a two-input gate, the standard SOP expression is Y = A'B' O a. NOR O b. NAND O c. OR O d. EX NOR O e. EX ORTask 2: DESIGN A 4-T0-1 LINE MULTIPLEXER BY USING THREE 2-TO-1 MUXS. CONSIDER THAT INPUTS ARE I3,12,11,10 AND SELECTIVE LINES S1,so ,GIVEN ACCORDING TO DEXCENDING SIGNIFICANCE ORDER. A) Write truth table. (Condensed version) B) Draw the logic diagram. (You can use the 2:1 MUX blocks or you can draw the circuit by using NAND & NOT GATES.) C) Simulate the circuit by using NAND & NOT GATES. Io Il (2:1 MUx BLOCK)