For an instruction set to be considered orthogonal, the computation of each set must be orthogonal. Only one value exists, and it stands alone. Explain.

Problem 1. This problem is about operand modes, in particular about memory addressing using the operand modes described in lecture and the textbook. The following shows the contents of a portion of the program memory (locations Ox10000 through 0x10040), and certain registers. All contents are 64-bit quantities. Address Memory Contents 0x10040 0x10038 0x10030 0x10028 0x10020 0x10018 0x10010 0x10008 0x10000 a. movq (%rdi), %rax b. movq (%rdi,%rsi), %rax 100 0x10040 200 25 0x10028 0x10020 c. movq 8(%rdi, %rcx, 4) %r8 d. movq -8(%rdi,%rsi), rbx 500 0x10018 2 Register Contents %rdi 0x10008 %rsi %rdx %rcx For each of the following instructions, say what value ends up in the destination register. Each instruction starts with the state shown above, i.e., the effects do not accumulate. 0x20 8 4

For example, suppose an instruction is not accepted and VA page 30 is generated. For the following use cases, a TLB controlled by software might be preferable than one handled by hardware:

Suppose we have two implementations of the same instruction set architecture. Computer A has a clock cycle time of 210 ps and a CPI of 2.2 for some programs, and computer B has a clock cycle time of 460 ps and a CPI of 1.3 for the same program. Which computer is faster for this program and by how much? Please and thank you

Suppose that we are developing a new version of the AMD Barcelona proces- sor with a 4 GHz clock rate. We have added some additional instructions to the instruction set in such a way that the number of instructions has been reduced by 15% from the values shown for each benchmark in Exercise 1.12. The execution times obtained are shown in the following table. a. Name Execution Time (seconds) Reference Time (seconds) bzip2 700 9650 SPECratio 13.7 1.13.2 [10] In general, these CPI values are larger than those obtained in previous exercises for the same benchmarks. This is due mainly to the clock rate used in both cases, 3 GHz and 4 GHz. Determine whether the increase in the CPI is similar to that of the clock rate. If they are dissimilar, why?

We can design stack architectures, accumulator architectures, or general-purpose register architectures. Explain the differences between these choices and give some situations where one might be better than another.