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For a cache memory of size 32 KB, how many cache lines (blocks) does the cache hold for block sizes of 32 or 64

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Concept explainers

Types of database architectures

A Database Architecture represents the Database Management System’s (DBMS) design (schema). The DBMS architecture makes it easy to understand the components involved in the database system and their relations. The DBMS architecture may vary based on the system on which it runs. Some systems contain both client and server machines whereas some run only on a server machine. Based on the architecture, the system can be classified as centralized, decentralized, or hierarchical.

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For a cache memory of size 32 KB, how many cache lines (blocks) does the cache hold for block sizes of 32 or 64 bytes?

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In designing a computer’s cache system, the cache block or cache line size is an important parameter. Which of the following statements is correct in this context? A smaller block size implies better spatial locality A smaller block size implies a smaller cache tag and hence lower cache tag overhead A smaller block size implies a larger cache tag and hence lower cache hit time A smaller bock size incurs a lower cache miss penalty
Suppose a computer using direct-mapped cache has 232 bytes of byte-addressable main memory and a cache size of 512 bytes, and each cache block contains 64 bytes.Q.) How many blocks of main memory are there?
What is the difference between a cache that is entirely associative and a cache that is directly mapped?
4. Suppose a computer using a fully associative cache has 2^24 byte of byte-addressable main memory and a cache of 128 blocks, where each block contains 64 bytes. a) How big in kilobytes is main memory? b) How big in bytes is cache? In kilobytes? c) How many blocks of main memory are there? d) What is the format of a memory address as seen by the cache, i.e., what are the sizes of the tag and offset fields? e) To which cache block will the memory address 0x01D8729A map?
For a direct-mapped cache with 64KİB data, 8-word blocks, and 32-bit addresses, answer the following questions: a) What is the number of blocks/lines in the cache? b) Identify the bits in the 32-bit address that are used as index bits? c) Identify the bits in the 32-bit address that are used as tag bits? d) What is the total number of bits in this cache (including tag field and valid field)? e) Identify the block number in the cache to which the following 32-bit memory address maps: Ox00003Z00 (Hexadecimal notation) where Z is the least significant digit in your student ID (written as a decimal number)
Exercise 1: Consider a word-addressable memory of 16 GB, where each word is composed of 128 bits. This memory is directly mapped to a cache of 1 MB composed of blocks where each block contains 16 words. a) What is length (in bits) of the address provided by the processor? b) What is the length (in Bytes) of one memory block? c) How many lines does the cache have? d) What is the length (in bits) of each of the TAG, LINE, and OFFSET? e) Which line in cache can hold the address 00000FOF?
Question 23 Some portion of cache system A represented below. The system is byte-addressable and the block size is one word (4 bytes). The tag and line number are represented with a binary numbers. The contents of words in the block are represented with hexadecimal. Tag 10 1000 0100 1001 10 1000 0100 1001 10 1000 0100 1001 10 1000 0100 1101 Line Number 0110 1101 0110 1110 0110 1111 B1 FF B8 A1 FF B8 B1 FF B8 A1 FF B8 B1 FF B8 0111 0000 1. What is the size of the main memory of this system? 2. What is the size of the cache memory of this system? 00 Word within block 2016 6116 C116 2116 01 10 11 3216 7216 C216 D216 4216 8216 4116 A216 E216 9216 5216 B216 3. If the CPU requests to read memory address A1 25 BA, what data does the CPU receive? 4. If the CPU requests to read memory address A1 35 C2, what data does the CPU receive? 5. If we access memory in the following order in cache system A: A1 FF B8 how many cache misses would occur for the data request?
c) The table below represents 5 lines from a 256 line cache that uses direct mapping with a block size of 4 words. Identify the address of the shaded data (F316). Word 10 Line# Tag Word Word 11 Word 00 01 110101 12 34 56 78 010101 54 32 6A D3 000111 29 8C ED F3 001100 33 A2 20 C8 4 110011 9A BC D8 FO