Find the error for the unit ramp input

What’s the difference between Moore and Mealy machines (FSM)? Design an FSM for the following sequential adder.

I need the answer as soon as possible

sovle given problem

Please help me with Q and Q'. Thanks

The Xi and Yi given in the figure show the inputs of each Full Adders inside the parallel adder. Shows the Select end (S) and the Hand bit (Carry in- Cin) of the arithmetic circuit. Find the output F and the Cout value for the Select bit, Hand bit , A and B values given below. S=1, Cin=1 and A=(0111)2 , B=(0111)2

For a 10-bit digital ramp ADC using 500 kHz clock, the maximum conversion time is 1. 2048 µsec 2. 2064 µsec 3. 2046 μsec 4. 2084 μsec Note:- Provide a clear text answer else ready for downvote 10 times.

mon De-emphasis is done: Select one: O a. none of the answers O b. after FM demodulation OC before FM demodulation O d. before FM modulation

Draw logical circuits for numbers 0 to 15 which if number is divisible by 3 output is 1 draw their k map and then in multiplexer

Do the following binary subtraction: 110000011.01011- 011110010.11111