empty page is available or the replaced page is not modified, and 20 percent of the time. What is the maximum acceptable page fault rat milliseconds if the replaced page is modified. Memory access time is 100 nanoseconds. Assume that the page to be replaced is modified 7 in registers. It takes 8 milliseconds to service a page fault if an Que 4.30. Consider a demand paged system. Page tables are held on effective access time of not more than 200 nanoseconds ?

empty page is available or the replaced page is not modified, and 20 percent of the time. What is the maximum acceptable page fault rat milliseconds if the replaced page is modified. Memory access time is 100 nanoseconds. Assume that the page to be replaced is modified 7 in registers. It takes 8 milliseconds to service a page fault if an Que 4.30. Consider a demand paged system. Page tables are held on effective access time of not more than 200 nanoseconds ?

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Please and thank you. An external event is sensed using polling with period P. It takes 100 cycles to processthe event. Processor frequency is 48 MHz. Before starting a new period, the previouspolling task should have finished. The relative deadline for processing an event is 10μs.(a) Determine the range of feasible polling periods? (b) Suppose now that an unrelated interrupt may occur and the interrupt has higher priority than the code for processing the polling event. Including all overhead, it takes 40 cycles to process the interrupt. The minimum time between two subsequent interrupts is T. Suppose that T is larger than 140 cycles. Determine the range of feasible polling periods.
Consider a paging system with the page table stored in memory.a. If a memory reference takes 400 nanoseconds, how long does a paged memoryreference take?b. If we add TLBs, and 95 percent of all page-table references are found in the TLBs,what is the effective memory reference time? (Assume that finding a page-table entry inthe TLBs takes zero time, if the entry is there.)
Consider a paging system with the page table stored in memory. A. If a memory reference takes 200 nanoseconds, how long does a paged memory reference take? B. If we add associative registers, and 75 percent of all page-table references are found in the associative registers, what is the effective memory reference time? (Assume that finding a page-table entry in the associative registers takes zero time, if the entry is there.)
Consider a paging system with the page table stored in memory. a. If a memory reference takes 50 nanoseconds, how long does a paged memory reference take? b. If we add TLBS, and if 75 percent of all page-table references are found in the TLBS, what is the effective memory reference time? (Assume that finding a page-table entry in the TLBS takes 2 nanoseconds, if the entry is present.
A computer uses virtual memory, and a new solid-state drive (SSD) as space for paging. Refer to the last ppt file. In the case presented there, the hard disk drive (HDD) required 25 ms to read in a page, and a rate of 1 page fault per 1000 references introduced a 250 slowdown. If the SSD offers a time of only 80 µs, what is the slowdown in performance caused by 1 pf per 1000 references (you are not concerned with dirty vs. clean pages). What is the maximum rate of page faults you can accept if you want no more than a 5% slowdown in execution using virtual memory? Know your metric prefixes and symbols for time: s for seconds, ms for milliseconds, µs for microseconds, ns for nanoseconds.
Consider a demand-paging system with a paging disk that has an average access and transfer time of 25 milliseconds. Addresses are translated through a page table in main memory, with an access time of 1 microsecond per memory access. Thus, each memory reference through the page table takes two accesses. To improve this time, we have added an associative memory that reduces access time to one memory reference if the page-table entry is in the associative memory. Assume that 75 percent of the accesses are in the associative memory and that, of those remaining, 10 percent (or 2.5 percent of the total) cause page faults. What is the effective memory access time?
Consider a demand-paging system with a paging disk that has an average access/transfer time of 50 ms. Addresses are translated through a page table in main memory, with an access time of 500 ns per memory access. Thus, each memory reference through the page table takes two accesses. To improve this time, we have added a TLB that reduces access time to one memory reference if the page-table entry is in the TLB. Assume that 80% of the accesses are in the TLB and that, of those remaining, 15% (or 3% of the total) cause page faults. We assume that the TLB access time is 20 ns. What is the effective access time?
(b) Consider a paging system with the page table stored in memory. If a memory referencetakes 200 nano seconds, how long does a paged memory reference take? If we add a TLB,and 75% of all page references are found in the TLB, what is the effective memory referencetime? (Assume that it takes zero time to find an entry in the TLB if it is already present).
please no chatgpt answer . Consider a demand-paging system with a paging disk that has an average access and transfer time of 20 milliseconds. Addresses are translated through a page table in main memory, with an access time of 1 microsecond per memory access. Thus, each memory reference through the page table takes two accesses. To improve this time, we have added an associative memory that reduces access time to one memory reference, if the page-table entry is in the associative memory. Assume that 80 percent of the accesses are in the associative memory and that, of those remaining, 10 percent (or 2 percent of the total) cause page faults. What is the effective memory access time? Consider the following page reference string: 1, 2, 3, 4, 2, 1, 5, 6, 2, 1, 2, 3, 7, 6, 3, 2, 1, 2, 3, 6. Assuming demand paging with four frames, Show which pages are resident under the LRU, FIFO, and Optimal replacement algorithms by filling out the following tables. How many page faults would occur…
Q1. Consider that the up system consists of two memory sections, the SRAM and the EPROM. The up clock system is 5 MHz and the bus cycle is equal to 4-clocks of the system clock pulses. For reading process, suppose that the waiting time of SRAM equals % waiting time of EPROM. If you know that, the total time requires for reading both memory types 1900 ns, what is the total waiting time requires for reading 128 bytes from the SRAM and the total waiting time requires for reading 512 bytes of EPROM? How many wait states require for reading each section of memory? Sketch the required circuit for generating the required number of the wait states.
Consider a swapping system in which main memory contains the following hole sizes in memory order: 10K, 4K, 20K, 18K, 7K, 9K, 12K, and 15K. Which hole is taken for successive segment requests of (a) 12K, (b) 10K and (c) 9K for Worst-Fit ?
Consider a memory system that generates 16-bits addresses and the frame size is 32-byte. At time To the status of the page table is given below. Page Table Entry Page # 1911 11 561 56 644 1068 1884 52 58 42 194 46 a) What is the maximum number of entries within a single page/frame? b) What is the maximum number of page table entries in the memory system? c) Using the given page table, determine the physical addresses for the following logical addresses. Write down the physical addresses in binary and decimal format. (i) (iii) 0101000010001011 1110101110010111 (ii) (iv) 0001100001100111 1110111011101001