е, calcu nds, exe ional br address stage c ng new n until th

Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
Section: Chapter Questions
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A CPU has 6 stages pipeline and runs at 1 GHz
frequency. Instruction fetch happens in the first
stage of the pipeline followed by instruction
decode, calculate effective address, fetch
operands, execute instruction and write back. A
conditional branch instruction computes the
target address and evaluates the condition in the
fourth stage of the pipeline. The processor stops
fetching new instructions following a condition
branch until the branch outcome is known. A
program executes 1010 instructions out of which
30% are conditional branch. If each instruction
takes 2 cycle to complete on average, then total
execution time of the program in seconds
Transcribed Image Text:A CPU has 6 stages pipeline and runs at 1 GHz frequency. Instruction fetch happens in the first stage of the pipeline followed by instruction decode, calculate effective address, fetch operands, execute instruction and write back. A conditional branch instruction computes the target address and evaluates the condition in the fourth stage of the pipeline. The processor stops fetching new instructions following a condition branch until the branch outcome is known. A program executes 1010 instructions out of which 30% are conditional branch. If each instruction takes 2 cycle to complete on average, then total execution time of the program in seconds
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