Draw an ASM chart for 2-bit up/down counter having a mode control input M. For M=1: Count up and M=0: Count down.

In verilog a counter must be developed from 0 to 9999 with a reset and parallel loading. The reset will be a button in charge of returning the count to 0 when pressed.For this practice, the implemented circuit will only use a 7-segment BCD converter module, which will have to be managed between the different 7-segment displays at a given frequency.

Question 4: Design and implement a minimal 5 modulo up counter. It counts from 0 to 4 and repeats. Design the circuit such that, if the counter enters into the unwanted states: 5, 6 and 7, it should jump into state 0 on the next clock pulse.

You are requested to design 16 x 1 multiplexer, meaning that this combinational circuit has 16 data inputs and produces a single output using selection bits. How many selection bits require?   Question 5 options: - 4 - 5 - 2 - 3

Problem 5 Write the entire VHDL code for a 64-bit synchronous counter that has a synchronous reset and an asynchronous preset. The preset value is 2048 and the reset value is all 0's. The 4 MSBS of the counter output also feeds a 4-1 mux. Show a schematic.

Question 9 How many input lines are connected to a multiplexer if it has Four control signals: 2 input MUX 4 input MUX 8 input MUX 16 input MUX

Draw the circuit of 2 bit universal register Selection line action SI SO 0. Shift left Parallel load Shift rignt No change (hold data) 1