Draw a chip layout/diagram for the image using a 74LS00 chip.

Q3) The Voltage-divider bias circuit shown below is to be designed to operate efficiently stabilized. Assume Ic(max) = 16mA and VRE= CC: 1) Find the values of R₁, R2, RE, Rc for maximum output voltage swing. 2) Draw the d.c. load line and a.c. load line on same graph indicating the Q point (VCEQ, Ico). 3) Determine the maximum value to which Vcc can be adjusted without exceeding a rating assuming PDmax=400m W Best wishes from me Barwan Ahmed 10 Vino C₁ R₁ www Vcc +20V R2 Rc C3 Si Tr B=100 Vou RL 1k

For an active low Set and reset waveform, how do you find the output waveform?

Regarding symbols used to illustrate transistors, a PNP transistor shows A. an arrowhead pointing into the transistor B. an arrowhead pointing out at the emitter. C. an arrowhead pointing out at the collector. D. no arrowhead