Design five-bit odd parity checkier

Redesign the right-shift register circuit of Figure 12-10 using four D flip-flops with clock enable, four 2-to-1 MUXes, and a single OR gate.

Convert the decimal numbers into signed 10-bit numbers. Signed and magnitude number 2's complement number Decimal l's complement number number 203 -77

4. EA sequence detector is to be designed to detect both the sequence 11 and 010 simultaneously. You will develop a state diagram with one input variable X and one output variable Z. The output is 1 if and only if the last two input bits are 11 or the last three bits are 010. Note that sequences may overlap. Sample input: 0010101111001101001 Sample output: 0001010111000100100 A) state with So and other states with S1, S2, S3, etc. Use a minimum number of states in Mealy model. Hint: please do NOT arrange all states in one line. Draw the state diagram. Label each arc with X/Z. Label the initial Start So B) Implement this state diagram using the minimum number of D flip- flops. Draw the state table for this state diagram. Assume that we use the following state assignments: So = 00; S1 = 01; S2 =10; S3 = 11. Qi Qo X Q1 (t+1) Qo (t+1) Z Complete the following three K maps. And then derive optimized C) Boolean expressions for the inputs to the D flip-flops and the output of the sequential…