Design a VHDL test bench to verify the functional operation of the system in the following figure using report and assert statements. Your test bench should drive in each input code for the vector ABCD in the order they appear in the truth table (i.e., "0000", "0001", "0010", ...). Have your test bench change the input pattern every 10 ns using the wait for statement within your stimulus process. Use the report and assert statements to output a message on the status of each test to the simulation transcript window. For each input vector, create a message that indicates the current input vector being tested, the resulting output of your DUT, and whether the DUT output is correct. NOTE: You will need to design the SystemJ.vhd system. Use a case statement to implement the logic. SystemJ.vhd F = EAB.C.D(4,5,7,12,13,15) ABCD Deliverables: Simulate your model and test bench using ModelSim. You are to upload your VHDL test bench file (SystemJ_TB.vhd) and a screenshot of your report outputs in the transcript portion of the ModelSim window (name it transcript_8_4_4.jpg) to the HW 8.4 Assignment Folder. Make sure to resize the transcript window so that I can tell if it is working.

3. Analyze the following design based on different values of X and Y and determine whether it can store a bit of information. If yes, form the characteristic table and show each of the set, reset, store, and complement actions if available. Otherwise, explain the problem with the design. DD

Write, and test using spim, an assembly language program that inputs acharacter string from the user (you can assume that the string will be at most 20characters, not including the zero byte delimiter), forms a new string that contains thecharacters of the input string, but in reverse order, and then outputs the new string.

Find the Boolean expressions and use theorem 1.1.1 to show that the two circuits are equivalent