Describe the timing diagram for output Q1 based on the following PLC ladder logic diagram where T001 is an ON Delay Timer given the input signals 11 and 12 as shown in the timing diagram below. TO01 11 12 V/H 1s TO01 M 10 11 12 TO01 Q1 1 0 1 0 1 0 1 0 11 ㅏ Trg T Q1 ΤΟΝ 5 Time (sec)

Assume a single cycle architecture were the maximum delay of in its instruction set is 10 ns and minimum delay is 2 ns, then the operational frequency is: a. 1GHz b. 500MHz c.100Mhz d. 50MHz e. 10MHz d. 5MHz f. 1MHz

Y=f(A,B,C)=(0,4,5)+don't care(2)

30) Coils labeled ( S ) and ( R )A) must appear in that order (S before R) in a ladder logic programB) may be used only in subroutines in programs for Siemens PLCsC) are Short and Repeated coils, used in timing programsD) may be used instead of a seal-in arrangement to provide latching