D En D | Next state of Q En 0 X No change 1 0Q= 0; reset state 1 1Q= 1; set state %3D (a) Logic diagram (b) Function table
D En D | Next state of Q En 0 X No change 1 0Q= 0; reset state 1 1Q= 1; set state %3D (a) Logic diagram (b) Function table
Chapter22: Sequence Control
Section: Chapter Questions
Problem 6SQ: Draw a symbol for a solid-state logic element AND.
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Question
The D latch of Fig. 5.6 is constructed with four NAND gates and an inverter. Consider the following three other ways for obtaining a D latch. In each case, draw the logic diagram and verify the circuit operation. Use four NAND gates only (without an inverter). This can be done by connecting the output of the upper gate in Fig. 5.6 (the gate that goes to the SR latch) to the input of the lower gate (instead of the inverter output).
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