*Construct a JK flip-flop using a D flip-flop, a two-to-one-line multiplexer, and an inverter. *Show that the characteristic equation for the complement output of a JK flip-flop is Q'(t+1)=J'Q'+KQ

We wish to design a digital system with two flip-flops, say B and C, and one 4 bit binary counter A, in which the individual flip-flops are denoted by A4, A3, A2, A1. A start signal S initiates the system operation by clearing the counter A and flip-flop C, and setting flip-flop B to one. The counter is then incremented by one starting from the next clock pulse and continues to increment until the operations stop. Counter bits A3 and A4 determine the sequence of operations: If A3 = 0, B is cleared to 0 and the count continues. If A3 = 1, B is set to 1; then if A4 = 0, the count continues, but if A4 = 1, C is set to 1on the next clock pulse and the system stops counting. Then if S = 0, the system remains in the initial state, but if S = 1, the operation cycle repeats. 1. Draw the ASM chart and the equivalent one flip-flop per state.