Consider a 2-way set associative cache with 32-bit address. The block offset takes 5 bits, the index takes 5 bits. Starting from power on, the following byte-addressed cache references are recorded. Address 4. 16 132 232 160 1024 30 140 3100 180 2180 1. What is the cache capacity? (number of bytes) 2.What is the status for each access? (hit, miss and replacement). 3.What is the hit ratio?

Consider a 2-way set associative cache with 32-bit address. The block offset takes 5 bits, the index takes 5 bits. Starting from power on, the following byte-addressed cache references are recorded. Address 4. 16 132 232 160 1024 30 140 3100 180 2180 1. What is the cache capacity? (number of bytes) 2.What is the status for each access? (hit, miss and replacement). 3.What is the hit ratio?

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter6: System Integration And Performance

Section: Chapter Questions

Problem 6VE

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