B. A certain gate draws 2 µA when its output is HIGH and 3.6 µA when its output is LOW. What is its average power dissipation if Vee is 5 V and the gate is operated on a 50% duty cycle? C. Convert a 10.2 V using 4 bits Successive-Approximation Analog-to-Digital Converter and sketch the conversion tree and sketch the conversion voltage variation as a function to time. Take the resolution 1 volt.

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Q2: Answer the following:
A. Determine the High-level and Low-level noise margins for 5 Volt CMOS Family.
B. A certain gate draws 2 µA when its output is HIGH and 3.6 µA when its output is LOW. What
is its average power dissipation if Vee is 5 V and the gate is operated on a 50% duty cycle?
C. Convert a 10.2 V using 4 bits Successive-Approximation Analog-to-Digital Converter and
sketch the conversion tree and sketch the conversion voltage variation as a function to time.
Take the resolution 1 volt.
Transcribed Image Text:Q2: Answer the following: A. Determine the High-level and Low-level noise margins for 5 Volt CMOS Family. B. A certain gate draws 2 µA when its output is HIGH and 3.6 µA when its output is LOW. What is its average power dissipation if Vee is 5 V and the gate is operated on a 50% duty cycle? C. Convert a 10.2 V using 4 bits Successive-Approximation Analog-to-Digital Converter and sketch the conversion tree and sketch the conversion voltage variation as a function to time. Take the resolution 1 volt.
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