Assume a sequence of assembly code as following: Add $s0, $t0, $t1 Sub $s1, $s2, $s0 Mult $s3, $s1, $s2 Div $s4, $t0, $t1 Lw $s3, 32($t0) Beq $s4, $s3, L1 Add $s0, $t0, $t1 Sub $s1, $s2, $s0 Mult $s3, $s1, $s2 Div $s4, $t0, $t1 L1: OR $s1, $s2, $s0 Add $s0, $t0, $t1 Sub $s1, $s2, $s0 If the address of first instruction (Add) is 2000, what is the address of Beq? If the Branch is taken ($s3=$s4) what will be the 7th instruction to execute and what is its address?
Assume a sequence of assembly code as following:
Add $s0, $t0, $t1
Sub $s1, $s2, $s0
Mult $s3, $s1, $s2
Div $s4, $t0, $t1
Lw $s3, 32($t0)
Beq $s4, $s3, L1
Add $s0, $t0, $t1
Sub $s1, $s2, $s0
Mult $s3, $s1, $s2
Div $s4, $t0, $t1
L1: OR $s1, $s2, $s0
Add $s0, $t0, $t1
Sub $s1, $s2, $s0
If the address of first instruction (Add) is 2000, what is the address of Beq? If the Branch is taken ($s3=$s4) what will be the 7th instruction to execute and what is its address?
The MIPS processor has a reduced instruction set. The MIPS instruction is 32 bits or 4 bytes (of 8 bits size). A word is the term used to refer to 32 bits. Words are always stored in consecutive bytes. A word's starting address is divisible by 4. Many of the instruction use register operands.
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