Accesses between various levels of the memory hierarchy are made faster by using buffers. List any potential buffers between the L1 and L2 caches and the L2 cache and the RAM for the given configuration

List the two main principles used in the design of memory hierarchies and explain them briefly. Briefly describe the read algorithm for reading data from a cache.

The latency of accesses made across various levels of the memory hierarchy may be minimized by the use of buffers. In the above configuration, please list any conceivable buffers that exist between the L1 and L2 caches, as well as between the L2 cache and the RAM.

Accesses between memory tiers may be made more quickly with the use of buffers. For the given architecture, please list any buffers that may exist between the L1 and L2 caches, and between the L2 cache and the RAM.