a) TLB hit, Cache hit b) TLB miss, Page table entry valid, Cache hit c) TLB miss, Page table entry valid, Cache miss d) TLB miss, Page table entry invalid (Page Fault), Cache hit (after the page fault is handled, the TLB is updated, and the access is restarted and the TLB now hits).

If a processor sends a cache-unfulfilled request while a block is being written back to main memory, should something happen?

What does write back mean in terms of cache? Group of answer choices   a. When an error occurs in memory, the cache is written back to the memory. b. When a bit in the cache is changed, the entire block is written to memory. c. When a line is evicted, the block it contains is written to memory.

To what extent does the specified log processing function have access to each field of a log entry? The following code estimates the average number of cache misses per entry while using 64-byte cache blocks and no prefetching.

To what extent does the specified log processing function have access to each field of a log entry? The following code determines the typical number of cache misses per entry while using 64-byte cache blocks and no prefetching.

Which fields in a log entry will the supplied log processing function access? How many cache misses per entry does the given function experience on average while using 64-byte cache blocks and no prefetching?

Assume that a block is being returned from the write buffer to main memory when the processor makes a partially completed request to the cache. The events should go as follows.

Which fields in a log entry will the log processing function that has been specified have access to? Assuming 64-byte cache blocks and no prefetching, the following code calculates the average number of cache misses per entry.

5. A computer has an L1 and L2 cache, backed up by DRAM which is backed up by virtual memory. The TLB and L1 caches have hit times of .5 ns. The TLB's backup is the page table in DRAM while L1 cache's backup is an L2 cache. The L2 cache has a hit time of 1.5 ns. DRAM has a hit time of 10 ns. Swap space has a hit time of 2,500,000 ns. The hit rates are: TLB: 98.8%, L1: 91.5%, L2: 97.7%, DRAM: 99.9998% and swap space 100%. What is the effective access time?

Which fields inside a log entry may be accessed by the log processing function that is specified. The following line of code calculates the average number of cache misses for each item, making use of 64-byte cache blocks and ignoring any opportunities for prefetching.