A logic circuit and three input waveforms A, B and C are shown in Figure2. Determine the following: Draw output waveform F.    Make truth table for output F.

For the following design, write Verilog code to describe it. Write testbench program to test the circuit for all possible inputs. INPUTS OR AND OR AND OUTPUTS

To select the ROM the address lines A10-A9 should be: A. 00 B. 01 C. 10 D.10

1. Consider the following two logic circuits. VDD A-6 B-d6 A-6 B-6 -6 -6 F VDD F t t A Circuit A Circuit B a. Do these two circuits implement the same logic function? If yes, what is that logic function? If no, give Boolean expressions for both circuits. b. Will these two circuits' output resistances always be equal to each other? c. Will these two circuits' rise and fall times always be equal to each other? Why or why not?

Design the following combinational logic circuit with a four-bit input and a three-bit output. The input represents two unsigned 2-bit numbers: A1 A0 and B1 B0. The output C2 C1.C0 is the result of the integer binary division A1 A0/B1 B0 rounded down to three bits. The 3-bit output has a 2-bit unsigned whole part C2 C1 and a fraction part CO. The weight of the fraction bit CO is 21. Note the quotient should be rounded down, i.e. the division 01/11 should give the outputs 00.0 (1/3 rounded down to 0) not 00.1 (1/3 rounded up to 0.5). A result of infinity should be represented as 11.1. A minimal logic implementation is not required. (Hint: start by producing a truth table of your design).

What logic function is performed by this circuit? VDD a. O d. e. A b. None OC AB AB A+B A+B O f. B AB M₁ M₂ M3 M4 F M5

Q1: Can you clearly show the answer to both parts of this question

draw the logic diagram using three basic 2-input logic gates    F=(A'+C) (A'+ C') (A+B+C'D)

Can the expert draw a full adder gate?