A computer or operating system will go through a series of steps whenever a TLB miss is located and fixed after having done so. Consider the performance in the most adverse circumstances.

What happens if the CPU has forwarding but the hazard detecting unit has not been developed?

Consider a paging system where the page table is stored in fast access registers (TLB) with an access time of 10 nanoseconds and a hit ratio of 80%. Memory access time is 100 nanoseconds (only one memory access). Assume that when a process generates a page fault, one of the processes pages currently in main memory will have to be replaced and that 60% of the time the page to be replaced has been modified. Assume that it takes 20 milliseconds to service a page fault if the page to be replaced has been modified and 10 milliseconds if it has not been modified. What is the page fault rate for an effective memory access time of 240 nanoseconds? Explain your steps and calculations.

Correctly arrange them in the order in which they are carried out to handle the interruption of a running user process by assigning a number from 1 through 9 to indicate the precedence order for the following steps.For example, 1 would indicate the first step in the process, 2 would indicate the second in theprocess and so on.