A byte-addressable system with 16-bit addresses ships with a three-way set associative, write-back cache (i.e., each block needs a dirty bit). The cache implements a true LRU replacement policy using the minimum number of replacement policy bits necessary to implement it, which means it requires 3 bits per set. The tag store requires a total of 264 bits of storage. What is the block size of the cache? (Hint: 264 28+23 and please also do not forget that aside from the tag itself, each block needs 1 valid bit, 1 dirty bit). =

The phrases "unified cache" and "Hadley cache" should be defined.

A byte-addressable system with 16-bit addresses ships with a three-way set associative, write-backcache (i.e., each block needs a dirty bit). The cache implements a true LRU replacement policy usingthe minimum number of replacement policy bits necessary to implement it, which means it requires 3bits per set. The tag store requires a total of 264 bits of storage. What is the block size of the cache?(Hint: 264 = 2^8 + 2^3 and please also do not forget that aside from the tag itself, each block needs 1valid bit, 1 dirty bit).

Suppose a computer using direct mapped cache has 236 bytes of byte-addressable main memory and a cache size of 1024 bytes, and each cache block contains 64 bytes. ⦁ How many blocks of main memory are there? ⦁ What is the format of a memory address as seen by cache, i.e., what are the sizes of the tag, block, and offset fields? ⦁ To which cache block will the memory address 0x13A4576B map?