a 5-stage pipeline (IF, ID, EX, MEM, WB) processor implementa nat does use bypassing/forwarding and does NOT use delayed branches. Assume that register reads can occur in the same cycle that the register write-backs are done. For the below code, how many stalls will be observed? Assume that the loop runs a total of 1024 times. Label: Idw r8, 0(r10) ; load into r8 from MEM[0+r10] add r9, r8, r7; r9 = r8 + r7 stw r9, 0(r12); store r9 into MEM[0+r12] addi r10, r10, 4; r10 = r10 + 4 addi r12, r12, 4; r12 = r12 + 4 bne r10, r11, Label; branch to Label if r10 != r11

On an ARM processor, assuming that [N-bit] = 0, [Z-bit] = 0, [C-bit] = 1, [V-bit] = 1, predict whether each of the following branch instruction is going to make the flow of control branch to the instruction labeled by NEXT (i.e., YES or NO). (These instructions are NOT executed one after the other one; instead, each instruction starts with the initial conditions given in the statement.) (a) BLS NEXT (b) BNE NEXT (c) BLE NEXT (d) BVC NEXT

:- We will be implementing a new instruction within the MIPS architecture. New instruction will decrement a Variable stored in a memory location and store the decremented value in a register (Rt). This new instruction will be called DECR. Its usage and interpretation is Usage: DECR Offset(4*Rs),Rt Interpretation: Reg[Rt]= Mem[4*Rs+Offset] - 1 Which blocks are used and which control signals are generated for this instruction. How would the Instruction code fields look like ? Do we need to add an extra hardware logic, explain ? (You may draw a simplified datapath flow)

CWDE converts word to double-word extending using EAX: AX . in which the sign of the 16-bit register, AX, is extended into the 32-bit register, EAX. What is the value for registers AX and EAX after executing the mnemonic opcode/operand instruction below? MOV EAX, 0 MOV AX, 0x429FCDA5 CWDE a. AX= CDA5 EAX=0000CDA5 O b. AX=CDA5 EAX=EFFFCDA5 O C. AX=CDA5 EAX=FFFE000 O d. AX= CDA5 EAX=FFFFCDA5