2. Design a 3 to 1 multiplexer using min-terms. Sketch your circuit design using only basic gates. 5 Homework #3 Name Please attempt all problems below. Half of your grade for this assignment will be based on completion of all problems, the other half of the grade will be based on your score on 2 randomly selected problems. 1. Please note that the switches are connected opposite to what you have seen in class. Thus, when a switch is open, a logic one is recorded, and when the switch is closed, a logic zero is recorded. In addition to the paragraph below, the company has also requested that the circuit be implemented on an FPGA. Please write a Verilog pseudo-code module that will implement your design. Note: pseudo- code only needs to contain the main components of the program, i.e., I inputs, outputs, assignment statements, etc. +5V SW1 SW2 SW3 SW4 fw fw Fwt Logic Circuit F SW1 and SW2 cannot be closed at the same time. SW3 and SW4. cannot be closed at the same time. F is high if two or more switches are pressed.

Question 1) If six NOT (inverters) gates are connected in series and the input to the first gate is a LOW (0) the output of the FIFTH. gate will be:

2. Design a 3 to 1 multiplexer using min-terms. Sketch your circuit design using only basic gates.

Objectives: To demonstrate the operation, characteristics and design of a saturated bipolar transistor switch Material Needed : 1- 2N2222A NPN transistor 1- 1k ohms resistor 1 - 4.7k ohms resistor 1- 470k ohms resistor ELECTRONIC WORKBENCH Procedure 1. Construct the circuit shown in Fig 1-1. The circuit receives its input from data switch SW1. You will monitor the output at the collector with a voltmeter. +Vcc Rc =1K Vo OUTPUT [SPACEBAR] to switch [Space] Rg=470k VCE SW1 Figure 1-1