please answer #3 in entirety. ALL PARTS 3. The exclusive NOR (XNOR) function can be expressed as follows:(a + b)' = XNOR(a, b) = Σm(0, 3)(a) Write the canonical SOP and POS expressions for the function.(b) Draw logic diagrams using AND, OR and NOT gates that represent the SOP andPOS expressions.(c) Assuming that the cost of a gate is 1+ number of gate inputs (same as what wasdiscussed in class), determine the cost of the SOP and POS logic diagrams inpart 3b. You must explain your answer by showing the cost of each gate in yourcircuit and the total cost.(d) Use Boolean algebra to show that the canonical SOP and POS expressions areequal. (e) Draw a logic diagram that implement the XNOR function using only NANDgates. You must explain you placement of bubbles and any additional gates.(f) Draw a logic diagram that implements the XNOR function using only NORgates. Again you must explain you placement of bubbles and any additionalgates.(g) Use Boolean algebra to show that your logic diagrams in parts 3e and 3f producethe POS or SOP expressions in part 3a. Here you must start with (xy)' for eachNAND gate with inputs x, y. Similarly, you must start with (x+y)' for each NORgate with inputs x, y.

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3. The exclusive NOR (XNOR) function can be expressed as follows: (a + b)' = XNOR(a, b) = Σm(0, 3) (a) Write the canonical SOP and POS expressions for the function. (b) Draw logic diagrams using AND, OR and NOT gates that represent the SOP and POS expressions. (c) Assuming that the cost of a gate is 1+ number of gate inputs (same as what was discussed in class), determine the cost of the SOP and POS logic diagrams in part 3b You must explain your answer by showing the cost of each gate in your circuit and the total cost.

3. The exclusive NOR (XNOR) function can be expressed as follows: (a + b)' = XNOR(a, b) = Σm(0, 3) (a) Write the canonical SOP and POS expressions for the function. (b) Draw logic diagrams using AND, OR and NOT gates that represent the SOP and POS expressions. (c) Assuming that the cost of a gate is 1+ number of gate inputs (same as what was discussed in class), determine the cost of the SOP and POS logic diagrams in part 3b You must explain your answer by showing the cost of each gate in your circuit and the total cost.

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Given the Boolean function f (A,B,C,D)-Em(1, 3, 9, 10) +Ed(0,2,8,13). a. Simplify the function using k-Map? b. Implement the function using standard gates? c. Implement the function using only NAND gates? d. Implement the function using only NOR gates?
1. Simplify the following Boolean functions by using Karnaugh map method. (a) F1(A, B, C, D) = Em(0, 1, 4, 5, 8, 9, 10, 12, 13) (b) F2(A, B,C, D) = Em(3,5, 7,8,9, 10, 11, 13, 15) 2. Design logic circuits of F1 and F, for A, B, C and D inputs. 3. Design Logic circuits of F1 and F2 by using only NAND gates as few as possible.
Q1: The following Boolean function Y=fA,B,C,D,E,F) =Em (0,5,7,8,9,12,13,23,24,25,28,29,37,40,42,44,46,55,56,57,60,61) Design the function with minimal logic gates using Karnaugh Map Method.
1. Obtain minimized SOP and POS for the following logic function: Z(A,B,C,D,E,F)=Em(0,1,2,3,4,7,9,12,14,16,17,20,23,26,27,28,31,34,35,36,37,39,41,46,49,52,53,57,60,61,63)+ Ed(6,22,38,42,43,44,45,50,51) Input type should be terms. Type how many variables and function, and choose Enter Names under Variable and Function Names Tab to change variable names Input terms format should match Logic Aid guideline. For example, for the function Z = Em(1,3)+ Σd(2,6) the input would be "1 3,,2 6." See "Help" for more information. In the simplification box select the correct SOP or POS form. In the simplification box use "Petrick-All Minimal Solutions" to obtain SOP and use "PI Chart-One Irredundant Solutions" to obtain POS.
Given the function F(w,x,y,z)=Σ(1,3,7,11,15)+dc(0,2,5,8)i. Write the function in conjunctive normal form ii. Minimize the function (DNF) using Karnaugh Map iii. Construct the logic circuit diagram for the minimized function.
The NAND logic gate is universal, meaning that using gate alone, we can implement any of the other logic gates. Find a way to define NOT, AND, and OR, using only NAND gates and the input variables I and y. (a) NOT(2) = (b) AND(x, y) = (c) OR(x, y) =
1) Givern the logic expression: F(A,B,C,D) = Em (0, 2, 5, 7, 8, 9, 13, 15) Use K-Map to simplify the expressions in SOP form and POS form and implement your circuit using any gates of your choice. Draw the K-map, the logic diagram and write down your expression neatly.
Examine the following monotone version of the Circuit-Value Problem: M-CVP: A circuit is called monotone if its internal gates are restricted to V-gates or A-gates. It is allowed that the input gates are either constants, variables, or negated variables. Given a monotone Boolean circuit C with one output gate and an assignment for the input variables b e {0,1}". Decide whether r(b) = 1? M-CVP { (C, b) | monotone acceptor circuit C is satisfied by b } . Show that M-CVP is P-complete by proving CVP
6. Given the function F = [I(0, 1, 4, 6, 7,8,9) + Md(5, 10, 11,12) a. [10] Write the equation for F in reduced SOP form b. [10] Draw the circuit using AND gates, OR gates and INVERTERS. 0 c. [10] Draw the circuit using only NAND gates and INVERTERS.
6. Given the function F = [I(0, 1, 4,6, 7,8,9) + Md(5,10, 11, 12) a. [10] Write the equation for F in reduced SOP form b. [10] Draw the circuit using AND gates, OR gates and INVERTERS.
3. a) What do you understand by static and dynamic hazards in a circuit, explain. b) Given the logic equation of a circuit as below: F= (a + c')(a' + b') Determine if this circuit has a hazard using K-Map. If there is a hazard, what type of hazard is that? Also write down the hazard free equation.
Logic Function F (x, y, z, w) = ∑ m (0,2,4,6,10,13) + ∑ k (8,12) as sum of minimers are given. (Note: There are terms that are not taken into account.) a. Obtain the Truth Table. b. Simplify with the Karnough Map approach. c. Draw the simplified Logic circuit with two input AND-NOT (NAND) gates. With how many apples you realized, what is your gain? Comment.