3. For the following sequence of instructions, assume that it is executed on a 5-stage pipelined datapath. If there is no forwarding or hazard detection, insert nops to ensure correct execution and explain why need to elaborate on how you get your answer. Without proper explanations, you will lose points.) add St5, St2, St1 Iw St3, 4 (St5) Iw St2, 0(St2) or St3, St5, St3 sw St3, 0(St5)

This is a block diagram of a microprocessor. Inta Rst 6.5 Trap Rst 7.5 Intr Rst 5.5 SID SOD Interrupt control Serial I/O control 8-bit internal data bus Accumulator Instruction decoder (8) Temp reg. (8) Flag (5) flip flops B C. Reg (8) (8) Instruction Reg Arithmetic decoder D (8) (8) and Reg Reg logic unit L (8) (8) Reg Register array machine Reg (ALU) (8) cycle encoding Stack pointer (16) Program counter (16) +5 V GND Power supply Incrementer/ decrementer address latch (16) Timing and control Reset CIk Gen Control Status DMA Address buffer (8) Data/address buffer (8) RD WR ALE S, S, IO/M Hold Clk out Hlda Reset out Ready Reset in A1s-Ag To Address bus AD-AD To Address/data bus

Help me with these computer architecture questions, please. I need help with questions 3 and 4.

For a FIQ interrupt technique, chaining and hooking must begin at the offset specified in the Interrupt Vector Table. It.?

Can you explain what would happen if an unapproved instruction is sent to VA page 30? In the following cases, a TLB controlled by software would be faster than one maintained by hardware: