3. Consider the following VHDL code. library use ieee.std logic 1164.all; entity pulsedet is port( signal clk, reset, pulse in: in std logic; signal pulse out: out std logic www w www. end pulsedet; architecture behavior of pulsedet is ww ww signal dffout : std logic vector(2 downto 0); begin dffs: process (clk, reset) begin if (reset = '1') then dffout <= "000"; elsif (clk'event and clk='1') then dffout (2) <= dffout (1); www www w w ww www ww www www www www dffout (1) wwww ww dffout (0) <= <= dffout (0); in; Mww www wwwww a wwwww www end if; end process; pulse out <= dffout (2) and not dffout (1): www ww ww ww end behavior; Draw a diagram of logic (combinatorial gates and flip-flops) that implements the VHDL code.

Assume that the system has eight 2-bit data inputs, A=a1a0, B=b1b0, C=c1c0, D=d1d0, W=w1w0, X=x1x0, Y=y1y0, Z=z1z0. There are also 2 control bits s1s0. The system computes A+B, C+D, W+X, and Y+Z when s1s0 equal to `11', `10', `01', `00', respectively. Use 1-bit 2-to-1 multiplexers and a 2- bit adder to implement this function. Please show how the inputs, multiplexers, and adder are connected. Label the inputs and select signals clearly. You don't need to show the details of the adder. (Hint: The adder has two 2-bit inputs E=e1e0 and F=f1f0. Each of E and F is generated by a 2-bit 4-to-1 multiplexer, which can be built using 1-bit 2-to-1 multiplexers.)

Please write your answers legibly and solve all steps.