3. Connect the full adder circuit shown in Fig. below using two half adders and OR gate, then record your data in table 2. Ci Si half-adder S C A half-adder Bi C Cin SW2 SW₁ B SWO 3 2 Table 2 INPUTS OUTPUTS Cin (SW2) B (SW1) A (SWO) Sum (LO) Cout (L1) 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 SUM Lo Cout L₁ 4. Connect the circuit as shown in Fig. below and record your data in table 3. i+1 What are the relations between the outputs of figures in step 3 and step 4? SW2 Cin SWO A SW₁ B 6 3 Table 3 10 SUM Lo 8 Cout L₁ INPUTS OUTPUTS Cin (SW2) B (SW1) A (SWO) Sum (L0) Cout (L1) 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1

For the chip below, determine the selection S2S1S0 that will generate a 1 at the Y output for the input conditions: I = 1z16l5|4|3|21110 = 00000100. Assume the device is enabled to have normal operation. U3 74LS151 EO- S2 S1 SO 15 14 H13 12 I0 YNO- 100 O_001 111 O 010 1654 3210 HHHH H H HE

answer both questions