2.1) Develop the RLL diagrams for the following Boolean equations : • F1 = A.B + A.B F2= swl. sw2.sw3. sw4 F3 = (sw1.sw2. sw3) + sw4 Y = (A.B.C + D ). (E.F)

Simplify using laws and rules of boolean algebraF = A’.B’.C’.D + A’.B’.C.D + A’.B’.C.D + A’.B.C’.D + A’.B.C.D + A’.B.C.D’ + A.B.C’.D + A.B.C.D

Find the Boolean expressions and use theorem 1.1.1 to show that the two circuits are equivalent

The NMOS circuit shown below implements a logic function where the voltage inputs are at Va, Vb, and Vc, and the voltage output is taken at Vout Va 9 Vb o 1.5 ΚΩ Q1 Q2 5 V ww Q3 D Vout Vc -O A. What is the circuit's logic operation? (multiple choice) a. b. c. d. Y = (AB)' + C' Y = (AB+C)' Y = (A + B)'C' Y = ((A + B)C)' B. The transistors in the circuit are identical, where VTH = 1 V and k = 2 mA/V2. Use the resistor model when the NMOS is in the linear mode of operation. If Vc = 5 V, what is the value of Rose, or the the drain-to-source resistance, of Q3? C. If Va = Vb = 0 V and Vc = 5 V, solve for Vout. ww

a. What are the 3 types of Verilog modeling? b. Draw the equivalent circuit for given Verilog Code. module circuit1 (x1, x2, x3, f); input x1, x2, x3; output f; not (notx1, x1); not (notx2, x2); not (notx3, x3); or (a, x1, x2, x3); or (b, notx1, notx2, x3); or (c, notx1, x2, notx3); or (d, x1, notx2, notx3); and (f, a, b, c, d); endmodule c. Differentiate between blocking and non-blocking assignment with simple example in Verilog?

. Design a logic circuit that controls an elevator door in a three-story building. The circuithas four inputs. M is a logic signal that indicates when an elevator is moving (M=1) or stopped (M=0).F1, F2 and F3 are floor indicator signals that are normally LOW, and they go HIGH only when theelevator is positioned at the level of that particular floor. For example, when the elevator is lined uplevel with the second floor, F2=1 and F1=F3=0. The circuit output is the OPEN signal which isnormally LOW and is to go HIGH when the elevator door is to be opened.