2. Design a 4-bit binary up counter (like the following state diagram) using JK flip flops. State diagram. eg. 00000001 Present state A; A₂ A₁ Ap 1111 (a) Draw the state table with the input values for J K flip flops Next state Flip-flop Inputs A3 A₂ A₁ Ap JA3 KA3 JA2 KA2 JAI KAI JAOK AD

Design a digital counter with the sequence: 0-5-10-15 and repeat. Use D FFs. (All unused states will be directed to the first count).

You are asked to design a circuit to detect if an overflow occurs when subtracting two integers represented in two's complement: Z= X - Y. Let Sz, Sx, and Sy be the sign bit for Z, X, and Y respectively, and they are fed as input to the circuit. Let O be the output bit of the circuit, whose value is 1 if an overflow happens, and 0 if otherwise. a) Build the truth table for O as a Boolean function of Sx, Sy, and Sz. b) Write the canonical expression (sum-of-product) for the Boolean function defined in the part a. c) Implement the Boolean expression defined in part b with a circuit by using AND, OR, and NOT gates. Draw the wiring diagram.

A UV flip-flop behaves as follows: • If UV = 00, the next state of the flip-flop is the complement of the present state. • If UV = 01, the next state of the flip-flop is 1. • If UV = 10, the next state of the flip-flop is 0. • If UV = 11, the next state of the flip-flop is the same as the present state. A Moore sequential circuit has one input X and one output Z. The circuit outputs Z = 1 if and only if the number of 1's received as inputs is a multiple of 3. Derive a state table for this circuit and realize the state table with UV flip-flops. Label your states S, and make the encoding the binary representation of i. For example, S₂ should correspond to Q1Q2 = 10.

1. The following figure shows the four-bit Adder. Your inputs for this combinational circuit are A = 3 and B = 5. What is the outputs S3, S₂, S₁, and So? You have to show how to get the outputs by indicating each carry bit. (Note: You should show all the steps to receive full credits) CA A3 FA B3 S3 C3 A₂ B₂ FA S2 C₂ A₁ B₁ FA S₁ C1 Ao Bo FA So Co

The D flip-flop is created by connecting two gated D latches serially, and inverting the CLK input to one of them. The following figure shows the internal circuit of D Flip-flop composing of two latches (L1: Master, and L2: Slave) and NOT gate. Answers the following questions. (Note: You should show all the steps) Complete the truth table below. CLK D CLK1 N1 CLK2 Q Q' 0 0           1 0           0 1           1 1

13. Using the I/O table, construct the appropriate Boolean expression, in CDNF, and a circuit for that expression x y z f(x,y,z) 1 1 1 1 1 100 10 10 1000 0 1 1 0 0 1 0 0 0 0 10 0001

following sequential circuit, provide equations for A* and B* construct a state table, and complete the timing trace until no state information remains. show the state table and timing trace and show the equations for A* and B*

4 bit 2’s Complement Multiplier INPUT A: 4 bit 2’s Complement numberINPUT B: 4 bit 2’s Complement numberOUTPUT: the product of A x B represented as a 8 bit 2’s Complement number   Do this:Build a 4 Bit UNSIGNED Multiplier as a subcircuit named UnsignedMultiplier use AND gate ,full and half adders for the circuit