- 2) What is the function of the transistór in the 555 timer circuit?
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- A Voltage to Frequency Convertor (VCF) consists of a voltage controller oscillator (VCO), a gate pulse generator, and an AND gate. If the output frequency to measured voltage of the VCO is 100. Calculate the measured voltage when 200 pulses are detected during 0.01 seconds.A 555 timer configured to run as an astable mode oscillator is shown in Figure 1. If the output is needed to have 30% duty cycle, i) Determine the required value of Rị if R2 = 7kN. ii) Determine the frequency of the output. iii) Draw the charging and discharging phase of capacitor Cext and its relation with the output waveform. ASsume Vcc = 12 V. +Vcc (4) |(8) R1 RESET Vcc (7) DISCH 555 D1 R2 (6) THRESH (3) OUT (2) TRIG (5) CONT GND :Cext 0.01 µF (1) 0.01µF Figure 1A 555 timer is configured to run in the Astable mode (Oscillalor) with Vcc=6v. If R1=2k Ohm andC=500 nF. What will be the value of R2 that gives? 1- The duty cycle = 70%. 2- The duty cycle = 50%. 3- The duty cycle = 30%. In all cases, draw the circuit diagram and compute the frequency of oscillation?
- What does the PWM duty cycle control in relation to the analogue output generated? The overall noise level in the analogue signal The PWM period The average amplitude of the analogue signal The PWM timebaseFor the circuit shown in Figure B23, a- 0.97, calculate the following: i. Collector current (Ic) ii. Collector-Base voltage (Ven) i. Emitter Current (I) iv. Base Current (In) Ic 2.5 kl Ouput 2.8V IB 10V Vec(a) Draw the circuit diagram of 2-bits flash (simultaneous) method analog to digital converter and explain its work briefly? (b) A 555 timer connected as astable multivibrator with R1=15 kQ, R2=100 k2, and Cl=0.02µf. Draw the circuit and determine the frequency and the duty cycle of the output square wave?
- For the BJT circuit shown in Figure b, find the operation point of the transistor. (use B=100 for BJT) Rc 9 k2 Vcc= 2.5 V Rp1 k2 Maximum file size: 51 FilesProvide an illustration and brief explanation of the 8051 external reset circuitry(comprising a resistor and capacitor).The most common technique to caneg analog to digital data is called Pulse Code Modulation(PCM). What are the 3 processes of a PCM? (in order)
- (d) In a certain clock generation circuitry, the input range of the PLL is 3MHZ – 6MHZ. If the input clock is 16MHZ. what are the best values for the divider and PLL setting to get 20MHZ at the output of the clock generation circuitry?(b) Answer each of the following: (i) Draw a circuit diagram for a synchronous MOD-6 counter. Draw a State transition Diagram for a MOD-6 synchronous counter. You diagram should include any possible temporary state(s) which may occur during operation or on power-up. (ii) (iii) Determine and clearly explain the operation of the circuit shown below: B Vcc Clock (c) In the context of a clocked flip-flop, answer each of the following: (i) Clearly describe what is meant by the te 'set-up time'. (ii) Clearly describe what is meant by the term 'hold time'.For the circuit shown in Figure B23, a = 0.94, calculate the following: i. Collector current (Ic) ii. Collector-Base voltage (VCB) ii. Emitter Current (Ie) iv. Base Current (IB) Ic IE 2.5 kN Ouiput 3.5V IB 12V VEE Vcc