2) For the IC 7495 used in item two of this experiment, what is the difference in operation between the two types of inputs (B1) and (A, B, C and D)? Explain that in detail. 3) Sketch the Q₁, QB, Qc and QD outputs for a 7495 shift register with the input waveforms shown in Fig. 16. Assume that the register is initially cleared.

Example 2-5. A 15-kVA, 2300/230-V transformer is to be tested to determine its excitation branch components, its series impedances, and its voltage regulation. The fol- lowing test data have been taken from the transformer: Open-circuit test (low voltage side) Voc 230 V loc= 2.1 A Voc = 50 w Short-circuit test (high voltage side) Vsc = 47 V sc = 6.0 A Psc 160 W Find the equivalent circuit parameters Xp,Rp,Xs, Rs, Xm,Rc

Which of the following statements are true about relative effect of quantization error values like the one computed in the previous problem? O The relative effect of quantization error depends on the voltage value currently being read in. O Relative effect of quantization error will seldom be a concern with strain gauge outputs because the output voltage is typically large. V A relative effect of quantization error value of around 100% means that the quantization error is as large as the signal itself. O A relative effect of quantization error value of around 50% means that the read-in signal will be quite noisy.

Given a 5-bit ADC with the following reference values Vref= -2V and 12V, what is the voltage represented by the output sequence 01010?

1What will be the state of a MOD64 counter after 90 input pulses if the starting state=000000?A.100100B.011010C.010110D.011100 2.A MOD 32 counter is holding the count 101112. What will the count be after 31 clock pulses?A.10100B.10010C.10000D.10110

Q2 - Pseudo-Random Number Generator a) The following circuit is a pseudo-random number generator which uses linear feedback shift registers to produce a stream of outputs. The XOR tap at index '1' is responsible for generating this sequence of outputs. Fill in the table for the outputs of the 4 registers after each clock cycle. The initial output state is already provided in the first row. You can stop when the output starts to repeat and just say that it is repeating. QO Q1 Q2 Q3 ID ClockEdge # Q3 Q2 Q1 QO 1 1 2 3 7 10 11 12 13 14 00

How do I solve the problem given below?

What is the maximum quantization error of an ideal 4-bit quantizer with a signed input signal having amplitude ±6? Answer should be with 4 decimal places.

A4 bit shift register, which shifts one bit to the right at every clock pulse, is initialized to values "1000" for Q0Q1Q2Q3. The 'D' input is derived from QO,Q2 and Q3 through two XOR gates as shown in below Fig. (a) How many clock pulses are needed for pattern 1000 reappears on Q0Q1Q2Q3 and write down logic table? (b) To what values should the shift register be initialized so that the pattern "1001" occurs after the first clock pulse? 88 9 Q D

Answer the D, E and F part