2) Assuming each instruction on a specific CPU must complete 7 stages from Fetch through Write Back that are one cycle each, (A) how many cycles would it take to complete 8 instructions without a pipeline, and (B) how many cycles would it take to complete the same 8 instructions with an idealized pipeline (no hazards) of those same 8 stages?
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- How does pipelining improve CPU efficiency? What’s the potential effect on pipelining’s efficiency when executing a conditional BRANCH instruction? What techniques can be used to make pipelining more efficient when executing conditional BRANCH instructions?_____ is a CPU design technique in which instruction execution is divided into multiple stages and different instructions can execute in different stages simultaneously.It is possible to design compilers and assemblers to order assembly language instructions such that a pipeline is exposed to the least amount of risk possible. One of the objectives of pipeline design is this. Do all assemblers and compilers rearrange instructions provided in assembly language in the same manner to achieve the best degree of productivity?
- Consider a multilevel computer in which levels are vertically stacked, with the lowest level being level 1. Each level has instructions that are m times as powerful as those of the level below it; that is, one level r instruction can do the work of m instructions at level r-1. However, n instructions at level r-1 are required to interpret each instruction at level r. Given this, answer the following questions: If a level 1 program requires k seconds to run, how long would the equivalent program take to run at levels 2, 3 and 4. Express your answer in terms of n, m, and r. What is the performance implication for the program if n > m? Conversely, what is the implication if m > n? Which case do you think more likely? Why?Compilers and assemblers may be configured to sequence instructions in assembly language in such a manner that a pipeline is exposed to the least amount of risk that is practically possible. This reduces the likelihood of errors occurring. Pipeline design should aim to achieve this as one of its aims. Do all assemblers and compilers rearrange instructions provided in assembly language in the same manner in order to achieve the best degree of productivity that is possibly attainable?Define pipelining in terms of increasing the speed of a processor, and then determine how many cycles it would take to run five instructions if each part of the machine required the same amount of time. In the absence of pipelining With pipelining, you may do (a), (b), (c), and (d), respectively.
- Can pipelined execution be attained if the times at which individual pipeline instructions run are not equal? Exactly what inefficiency have you noticed?Suppose that a task on the ARM computer runs 256M instructions during its execution. The total time it takes to execute an instruction is 120 ns. We make the assumption that the work to be performed by one instruction can be divided into an arbitrary number of pipeline stages. Now complete the following problems. b. Now suppose that the pipelining register delays and processor control overhead adds 10ns to the latency of each pipeline stage. (So, for example, if there are four pipeline stages, each instruction will have an execution latency of 160ns and the pipelined machine produces 1 instruction every 40ns.) What is the maximum speedup that can be obtained through pipelining? Assume there are no hazards (ideal pipelining).If the execution time of pipeline instruction execution is not balanced, what inefficiency must be introduced to allow the piplelined execution to occur? Describe this inefficiency.
- Compilers and assemblers can be programmed to sequence assembly language instructions in a way that poses the least risk to a system's pipelines. In fact, achieving this is a primary focus when planning a pipeline. Is it true that all assemblers and compilers rearrange the order of assembly language instructions in the same way?NOTE: "Exekveringstid(ms)" means execution time or burst time in milliseconds Assume that a system with a CPU at one time has the following processes queued in the CPU's READY queue: Calculate the waiting time for the seven processes: 1) If FCFS is being used 2) If LRU is being used 3) If RR with time quantum of 8msCompilers and assemblers may be programmed to sequence instructions in assembly language in such a way that a pipeline faces the least amount of risk feasible. This is one of the goals of pipeline design. To reach the highest possible level of productivity, do all assemblers and compilers rearrange instructions written in assembly language in the same way?