14. The shift register in Figure 8–54(a) has SHIFT|LOAD and CLK inputs as shown in part (b). The serial data input (SER) is a 0. The parallel data inputs are Do = 1, D1=0, D2=1, and D3=0 as shown. Develop the data-output waveform in relation to the inputs. Do D¡ D2 D3 1 0 10 CLK SHIFT/LOAD SRG 4 Data SER SHIFT|LOAD out CLK (а) (b)

14. The shift register in Figure 8–54(a) has SHIFT|LOAD and CLK inputs as shown in part (b). The serial data input (SER) is a 0. The parallel data inputs are Do = 1, D1=0, D2=1, and D3=0 as shown. Develop the data-output waveform in relation to the inputs. Do D¡ D2 D3 1 0 10 CLK SHIFT/LOAD SRG 4 Data SER SHIFT|LOAD out CLK (а) (b)

Introductory Circuit Analysis (13th Edition)

13th Edition

ISBN:9780133923605

Author:Robert L. Boylestad

Publisher:Robert L. Boylestad

Chapter1: Introduction

Section: Chapter Questions

Problem 1P: Visit your local library (at school or home) and describe the extent to which it provides literature...

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