12) Study the ladder logic program in the figure below and answer the questions that follow: a. What is the purpose of interconnecting the two timers? b. How much time must elapse before output PL is energized? c. What two conditions must be satisfied for timer T4:2 to start timing? d. Assume that output PL is on and power to the system is lost. When power is restored, what will the status of this output be? e. When input PB2 is on, what will happen? f. When input PB1 is on, how much accumulate. Ladder logic program Output PB2 L2 T4:1 Inputs (RES) L1 T4:2 PB1 (RES) PL PB2 -RTO PB1 RETENTIVE TIMER ON T4:1 EN 1.0 2900 CON) Timer Time base Preset Accumulated -RTO PB1 T4:1 RETENTIVE TIMER ON Timer Time base T4:2 (EN) 1.0 1780 DN Preset (Na) CON) Accumulated T4:2 PL HE DN

5

Solve only 4 please

Construct a timing diagram with all the possible inputs and output for the logiccircuit shown in Figure Q2(d).

Which answer is correct?

What is setup time and hold time for a sequential circuit. Draw schematically a timing diagram showing the setup time and hold time for an input data signal, and draw the corresponding output data signal along with a clock signal

24)A PLC scan cycle contains each of the following operations EXCEPT A)read inputs B)perform diagnostics & communication C)execute logic D)compile installed ladder logic program

Plc

1. A synchronous finite state machine contains a single 'Serial Data' input (SD) and two outputs (S and 7). Output S should be active for one clock pulse every time the input sequence 11010 is detected and output T should be active every time the input sequence 11001 is detected. The functionality of this machine may be partially represented by a timing diagram as shown in Figure 1. Clock a) SD S T Figure 1: Synchronous finite state machine timing diagram Derive the Moore model state diagram for this machine. Hint: ensure that the machine operates correctly even if the bit pattern is preceded by sub-sections of the pattern. [5]