12-bit data to the left by 0, 1, 2, or 3 positions, the output of this shifter at *$150=10 is X11X10 X/XI 0123-1-2-3 0123 yıl yo yo ys X7X6 X5 X4 0123-1-2-3 0123 y?yeys ya X3 X2 X1 X3 0123-1-2-3 0123 y3y2 yi yo ОЕ Y=X9X8X11X10 X5X4X3X2 X1X0X7X6 O Y=X8X11 X10X9X4X7X6X5 X0X3X2X1 O Y=X8X7X6X5 X4X3X2X1 X0X11X10X9O None of them O Y=X9X8X7X6 X5X4X3X2 X1X0X11X10

Assume that the system has eight 2-bit data inputs, A=a1a0, B=b1b0, C=c1c0, D=d1d0, W=w1w0, X=x1x0, Y=y1y0, Z=z1z0. There are also 2 control bits s1s0. The system computes A+B, C+D, W+X, and Y+Z when s1s0 equal to `11', `10', `01', `00', respectively. Use 1-bit 2-to-1 multiplexers and a 2- bit adder to implement this function. Please show how the inputs, multiplexers, and adder are connected. Label the inputs and select signals clearly. You don't need to show the details of the adder. (Hint: The adder has two 2-bit inputs E=e1e0 and F=f1f0. Each of E and F is generated by a 2-bit 4-to-1 multiplexer, which can be built using 1-bit 2-to-1 multiplexers.)

Q1. 12.11 Redesign the right-shift register circuit of Figure 12-10 using four D flip-flops with clock enable, four 2-to-1 MUXes, and a single OR gate. Qo 01 10 00 01 01 10 D O D O DQ 10 D. D D Do Sh 7. CLK 72°F Sunny

14--17) Given the unusual circuit below constructed of full and half adders, determine the 5 bit output of the circuit for each of the given 2 bit values for A and B. A, B, Ao Bo НА FA НА FA 14) A = 10 B = 11 16) A = 01 B = 10 15) A = 11 B = 10 17) A = 10 B = 01

Design a circuit that displays the letters A through J on a seven-segment indicator. The circuit has four inputs W,X, Y, Z, which represent the last 4 bits of the ASCII code for the letter to be displayed. For example, if WXYZ =0001, "A" will be displayed.

10. For the register shown below, if Do=1, D₁=0, D2=0, D3=1. After three clock pulses, what are the data outputs? Parallel data inputs CLK Do D₁ D₁ Dy D D D D Qo Q2 Parallel data outputs