1. Provide the outputs of Q3, Q2, Q1, and Q0 by completing the timing diagram of the Parallel-in/Serial-out Right Shift Register. Assume that all outputs (Q3, Q2, Q1, and Q0) are 0 initially. The functional truth table and input signals are provided below: CK w n ●●● En Do Inputs En of 0 D3 1 Q₂ X Q₁ Q3 CK O 1 X NS + + otot ot D₂ D₁ Do Q₁ Qo Do Q₂ Q₁ Qo Q₂ Q₁ Qo Load Right shift Hold

3. The timing diagram below is for the 8-bit register block shown. Complete the timing diagram by filling in the output (q) signal. load q(N-1.0)+ cik cir Input(N-1.0) cik Register cir load input 45 A3 4B FF 44 01 02 CA 66 7A 98 9

29#3 I am trying to understand how to think these problems through and how to do them. Please write step by step explanations so I can follow with the thought process! Thank you! :)

Please write nicely.