1. Implement the given Boolean function in (a) NOR and (b) NAND gates only. Use two-input gates only. F = (A' + B'C') D' + BC (D + E') (C'D+ AD')
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- Task 6: Simplifying Boolean functions in EWB using the logic converter Simplify the following Boolean expression in EWB using the logic converter F (A, B, C) = AB'C'+ A'B'C'+ A'BC'+ A'B'CLogic Gates:* 7404LS (NOT)* 7408LS (AND)* 7432LS (OR)* 7400LS (NAND)* 7402LS (NOR)* 7486LS (EX-OR)Or you can use 74HCxx versions. Task 2: 4 INPUT PRIORITY ENCODERa) Write the truth table.b) Find the outputs in terms of min terms using minimal expression.c) By using K map, find the simple/simplest expression of theoutputs.d) Draw the circuit diagram. (Simulation design will be accepted.)e) Simulate the circuit & explain your results. (Please do notdesign separate simulations for each output. You should design ONEsimulation including all inputs and outputs.)(c) Figure Q3(c)(i) shows a register and Figure Q3(c)(ii) shows the input waveforms (CLOCK and Data in) to the circuit. A1 A9 A10 A2 Function generator A3 A11 A12 AS A13 A6 A14 A7 A15 Data in Bop.7) ip.r 82p.7) Logic analyser U1 U2 U3 U4 UO 6. 1. 6 1 6 INVERTER 3 CLK 3 CLK oCLK CLK 5 K K 5 K K 4027 Clock Function generator Figure Q3(c)(i) (i) Determine the type of register as shown in Figure Q3(c)(i).
- Draw the AND and OR gate logic diagram of the expression. X=[[K(K+L) +M] Logic diagram using AND-OR gates Redraw the circuit using positive NOR gates. Logic diagram using positive NOR gates3- A-) Implement the Boolean function (F) with a 4 X1 multiplexer and two-input-NOR gates. Connect inputs A and B to the selection lines. The input requirement for the four data lines will be a function of variables C and D. These values are obtained by expressing F as a function of C and D for each of the four cases when AB = 00, 01 ,10 and 11. B-) Implement the Boolean function with a 8 X 1 multiplexer. Connect inputs A,B and C to selection lines. F(A, B, С, D) - 2 (1, 3, 5, 9, 10, 14, 15) А So В S1 4 x 1 MUX 1 Y F 2 3. Simplify the following Boolean algebraic expressions and draw a block diagram of the circuit for each simplified expression using AND OR and NOT gates. (a) AB’C’ + A’B’C’ + A’BC’ + A’B’C (b) A’BC + AB’C + A’BC + ABC’ + AB’C’ + A’BC’ + A’B’C’ (c) (A + B + C) (A + B’ + C’) (A + B + C’) (A + B’ + C)
- Electrical Engineering A B Out 0 Cout Please read. In Verilog only uses reg variables and model each gate using an always block. Describe it as a Verilog module with inputs A, B, Cin and outputs Outo and Cout. Introduce as many reg variables as needed and model each gate using an always block. i.e. Combinational logic is described as procedural blocks, but still maintaining concurrency. Also, write all the gates inside a single always block and see whether you can order their evaluations to obtain the correct results for Out_0 and Cout signals.1. a. i. Draw the gates required to build a half adder are ii. When simplified with Boolean Algebra (x + y)(x + z) simplifies to : iii. The output of a logic gate is 1 when all its inputs are at logic 0, the gate is either :Simplify the given Boolean expression and then draw a logic circuit using NOR Gates. X (A, B, C, D) = AB’C’ + AC + A’CD’
- Determine the truth table for the following logic circuit. Then identify the type of logic gate using Boolean algebra. O +Vcc R23 ER O O/P Q1 Q2 BO3-) Make the following Logic Function with Karno diagram in Max.term form the simplest and give the final form; Draw with 2 Input NOR gates only F(A,B,C) = A. (B.C + B'.C) + B. (A'.C' + A.C') + (A.B'.C')Consider F(A,B,C) = AB'C + B'C' + A'BC + A'C' 1. Determine how many logic gate inputs would be needed before any simplification. Do not count inputs to NOT gates 2. Use Boolean algebra rules to get the most simplified expression of F(A,B,C). Then determine how many logic gate inputs would be needed after simplification. Again, do not count inputs to NOT gates. 3. Expand the original expression into its canonical SOP representation. 4. Fill out the K-map below using the SOP canonical representation. Group the 1-cells according to the K-map simplification rules. Translate each group into its product term, OR these product terms together, and verify that the expression you get matches the one in Step 2. 5. Draw two circuits in CircuitVerse, one from the original expression for F(A,B,C), the other from the simplified expression in Step 2 or Step 4. Connect the inputs to both circuits, but separate their outputs. Verify through simulation that these two circuits are indeed equivalent. Take…