3.3.4 Now Serving Dispay | Alazone Smith DE – 3.3.4 Mr. Woods March 13, 2013 Directions: All words in blue italics must be replaced with your own information and changed to black non-italic font. Abstract: The Purpuse of the 3.3.4 Now serving project was to gather the information we learned in previous projects such as, the 60 second timer, and other various activities involving asynchronus counters. Also, from this project we would gather valuable information about the 74ls193 and 74ls163 counters, while at the same time showing our knowledge of the circuit implementing we had already learned.We were suppose to Continue progress on the 60 second timer which counted from 00 to 60 on the 7-segement display, then reset once it …show more content…
But, also to possibly gain extra experience Breadboard prototyping was optional. Technical Drawings: Multisim The Multisim part of the project was developed using the similar implementation of the 60 second timer, but to allow the larger count of 99 and to control the single manual count I had to replace the previous gates with the 74LS193N and the 74LS163N. I was also meant to implement a switch that would allow me to reset the Counter at any point in time (end of the day for now serving counter), but sadily I was unable to implement this do to my time constraints, also I had a little difficulty fixing the the small problems I already had. But as you can see the input circuiting and output circuiting are both all in order. PLD-FPGA The FPGA/ PLD implementing part of this project was easy after I had established the Multisim part of it, but all I had to do was refind all the circuits in the PLD listing and re-create the same file piece by piece. Conclusion: For the 3.3.4 Now Serving project I believe I did fairly well in using majority of my own knowledge and experiences to develop a working Multisim and a partially working PLD design. I feel this way because of my exstensive rigor to constantly use the Guess and Check process, form which I was able to satisfy majority of my constraints and express the skills I
As these flip-flops have a positive edge trigger for the clock input, this means every time the clock input goes from LOW to HIGH, it triggers the flip-flop, updating the Q output to whatever the D input is, assuming the SET and RESET inputs of the flip-flop are both inactive, which they are in this circuit (Digital Electronics, 2014). At the start, the D input will be HIGH, because D is connected to the inverted Q output (PyroElectro, 2013). However, the 555 timer has a HIGH output at the start, but due to the fact the flip-flop triggers when the clock input goes from LOW to HIGH, the counter still starts off counting from 0, because it takes one count for the clock to go back to LOW then to HIGH again. As the clock counts, every second count of the previous flip flop will cause the next flip-flop to change state. Thinking back to simple binary theory, this makes sense. As a digit in binary is double the previous one, every second time the previous digit changes state, the next digit should change state once. As this is a four bit counter, once the fourth digit changes state from HIGH to LOW, the counter resets, and counts from zero
Use lab03 as the project name and lab03_part01 as the top-level design entity for this project. Click Next.
1 bit counter can be used as the control block which toggles every time the system/chip starts. For a 10-year lifespan, it would be ~50% (5 years) total time for either 0 or 1 as the output bit statistically.
Now that you have completed your project, you need to look back at your proposal and compare it with your finished product. You need to answer the following questions as completely and honestly as possible.
List the inputs, any processes/calculations, and outputs. Use the same valid variable names you used in Step 1.
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