HW7-memory_concepts

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Electrical Engineering

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Jan 9, 2024

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ECEN 340 Homework 7 – Memories (84 points, 4 points each) Name: _____Morgan Yang__________________________ Memory with bi-directional data busses present new challenges to the engineer. It is also important to be able to understand the code written by another engineer. The Verilog modules at the end of this assignment are to be used to answer the following questions: 1) How many multi-dimentional memory arrays are instantiated in this design as a module? T wo . The input memory array and the output memory array. 2) What type of memory arrays are used in this design? a) Static Random Access Memory (SRAM) with a single 3-state data bus b) Dynamic Random Access Memory (DRAM) with dedicated input and output data busses c) Read Only Memory (ROM) d) Static Random Access Memory (SRAM) with dedicated input and output data busses 3a) When using memory with bi-directional (3-state) data buses, how is contention avoided? The output buffers of the memory need to be set to a high impedence when data is written to the array. The write path needs to be set to high impedence when reading from the memory. 3b) How many bi-directional (3-state) busses exist in this design? Two 3c) Which signals are used to control the 3-state busses in this design?

4) Besides using memory arrays, this design uses discrete memory elements (flip-flops) to complete specialized tasks. How are flip flops used to: a) Debounce a push-button switch. A push button switch can create multiple signals, so flip-flops and latches can be used to ensure that only one of those signals is acted on to store a given value to the memory arrays. b) Remember the last button press (left and right pushbuttons). In thw program, there is a conditional statement within the always block. The flip-flops can remember button presses in congruence with the clock signals. When a button is pressed, that signal is sent and won’t change again until the next input comes with a new clock cycle c) Increment/decrement a memory address. The inc_addr and dec_addr signals are fed into flip flops to generate a depayed version of these signals called inc_addr_tm1 and dec_addr_tm1. 5) What happens when you: a) Press and release the left button by itself? To select the input memory banks b) Press and hold the left button by itself? Always select the input memory banks c) Press and release the right button by itself? To select the output memory banks d) Press and hold the right button by itself? Always select the output memory banks

e) Press the top button by itself? To increment memory addresses d) Press the bottom button by itself? To decrement memory addresses e) Simultaneously press the left and center buttons? To execute an “inc_addr_all” operation d) Simultaneously press the right and center buttons? To increment address pointer at 100MHz starting from the current location, perform a math function on the input memory data, and then store the result into the second memory bank. e) Simultaneously press the top and bottom buttons? To clear the memory address to zero 6) What is written to the output memory? The output data is the sum of the first 8 bits and the last 8 bits of the addressed input memory. 7) What math operation is performed when writing to the output memory? Addition 8) What is the execution rate of the math operation? 100 MHz 9) Why do you think the output memory address (OM_addr) must be delayed by one clock cycle relative to the input memory address (IM_addr)? The output memory address is delayed by one clock cycle because the clock needs to get through an additional full cycle in order for the input to be acted upon. This ensures there are no contention conflicts

module memory_top( input clk, //100MHz clk. input [15:0] sw, //Data for input memory. input btnC, //Used with other buttons to select an operation input btnU, //Increment the memory address by one. input btnD, //Decrement the memory address by one. input btnL, //Select the input memory bank. input btnR, //Select the output memory bank. output [3:0] an, //The anode drivers for the 7-seg display. output [6:0] seg, //The 7-segments. It is used to display the data in memory. output dp, //The decimal place on the 7-seg display. output [15:0] led //The 16 leds are used to display the address information and the mode information. ); wire [15:0] Ibus_data; // Data for the input memory bank. wire [15:0] Obus_data; // Data for the output memory bank. wire [15:0] op_data; // The results of a math operation on the two halves of the input memory bank. wire disp_ID_ODb; // Ibus_data will be displayed when this signal is true, Obus_data when it is false. reg [15:0] disp_data; // data to be displayed (Ibus or Obus). wire left, center, right, up, down; // debounced buttons wire [3:0] IM_addr; // address for the input memory

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