Lab 5 - ECE 385_ Digital Systems Laboratory (Spring 2022) - Illinois Wiki

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5/15/23, 11:14 PM Lab 5 - ECE 385: Digital Systems Laboratory (Spring 2022) - Illinois Wiki https://wiki.illinois.edu/wiki/display/ECE385SP22/Lab+5 1/6 Dashboard / … / Labs Created by Julieanne Chapman, last modified by Cheng, Zuofu on Mar 03, 2022 Lab 5 Simple Computer SLC-3.2 in SystemVerilog In this experiment, you will design a simple microprocessor using SystemVerilog. It will be a subset of the LC-3 ISA, a 16-bit processor with 16-bit Program Counter (PC), 16-bit instructions, and 16-bit registers. For a general understanding of the LC-3 CPU, see Patt and Patel (ECE 120 textbook). Assignment Read the Lab 5 description in the lab manual and complete the Lab 5 Pre-Lab before the lab section. Work on Lab 5 report and Lab 6 Pre-Lab after the Lab 5 Week 2 section. Demo Week 1 Simulation of PC loading into MAR and PC incrementing. (1 points) Simulation of MDR loading into IR. (1 points) Correct FETCH operation on the board, showing IR on the hex displays. Must use the physical on-chip memory (slc3_sramtop.sv with instantiateram.sv). (1 point) The above demo is due in Week 1. No makeup demo is allowed in Week 2. The demo points and the workloads of week 1 and week 2 are not evenly distributed. Week 2 - Note that all demo points are on the physical DE10-Lite FPGA board. No points are given during demo for simulations. Basic I/O Test 1. (1.0 point) Basic I/O Test 2. (1.0 point) Self-Modifying Code Test. (1.0 point) XOR Test (1.0 point) Multiplication Test. (1.0 point) Sort Test. (1.0 point) Correct “Act Once” Behavior. (1.0 point) Reserve your demo slot by enter your NetID(s)

5/15/23, 11:14 PM Lab 5 - ECE 385: Digital Systems Laboratory (Spring 2022) - Illinois Wiki https://wiki.illinois.edu/wiki/display/ECE385SP22/Lab+5 2/6 Current Demo: Final Demo (in- Find your section below and sign up for a d by entering you and your partner's NetIDs Note: do not sign up prior to the Wednesda available demo slots will not be finalized un when the demo schedule updates. Zoom room for demos are found on your TA Remember to zip and upload your code to Landing Page ME YD HL DJ DT GL HW For details, refer to the Week 2 Test Programs Documentation below. Resources Appendix A - Appendix A of 190 textbook. Instruction set reference. Appendix C - Appendix C of 190 textbook. Design your state machine as shown in this appendix, and design your datapath. (See below for updated diagrams and tables.) ECE 120 Control Signals Reference (from Prof. Lumetta's notes - note that this also refers to the full LC-3) Provided SV files in (.zip) archive ( updated 03/02/2021 updated naming to Lab 5 instead of Lab 6, changed slc3.sv DRMUX and SR1MUX to be 1 bit instead of 2) - Includes 5 parts in 8 files: The top level entity ( slc3_sramtop.sv for synthesis ) and ( slc3_testtop.sv for simulation ) depending on whether you are using the test_memory dummy RAM or on-chip memory.

5/15/23, 11:14 PM Lab 5 - ECE 385: Digital Systems Laboratory (Spring 2022) - Illinois Wiki https://wiki.illinois.edu/wiki/display/ECE385SP22/Lab+5 3/6 The SLC-3 module ( slc3.sv ) - you need to design the datapath module. Remember to comment and uncomment some codes for week 2. See comments for details. Control Unit ( ISDU.sv ) skeleton - you need to fill in the control unit for week 2. The required memory controller files ( Mem2IO.sv and instantiateram.sv ) (You don't need to modify them, but are strongly recommended to understand how they work.) Simulation memory ( test_memory.sv ) is meant to be in place of physical on-chip memory in simulation. (requires SLC3_2.sv and memory_contents.sv ) It only works in simulation and will be synthesized into a blank module in synthesis. Week 2 Test Programs Documentation ( updated 2/13/2018) - Details about the tests you will need to run on your CPU during week 2 of the demo. Tutorial on Instantiating Megafunctions (you will need to create an on-chip memory Megafunction for your RAM) Updated diagrams and tables: Updated Block Diagram - Shows how the physical SRAM should be connected to the SLC microprocessor. Note that this is no longer accurate when using the MAX10 on-chip memory, though it is provided for you as a reference/starting point for modification. Updated State Machine - LC3 state machine with extra states removed and added pause states ( JUST TO REMIND: You cannot use the state transition diagram from the Lab Manual directly(i.e. without modification) because it is NOT what you actually implemented (you don't have R signal, and you have, say, 33_1, 33_2 ...). Please draw one by yourself (or modify based on the given diagram). There are many tools you can download or find on EWS to help you draw the diagrams.) Updated Data Path Control Signals - Similar to Table C.1 in Appendix C. Shows what values each control signal can take and their meanings. For the full datasheet on using Embedded Memory Blocks, consult the Max10 Embedded Memory User Guide Useful Readings Cummings, Clifford E. "Nonblocking assignments in verilog synthesis, coding styles that kill!." SNUG (Synopsys Users Group) 2000 User Papers (2000). Cummings, Clifford E. "State machine coding styles for synthesis." SNUG'98 (Synopsys Users Group San Jose, CA, 1998) Proceedings . 1998. Sutherland, Stuart. "SystemVerilog Saves the Day—the Evil Twins are Defeated!“unique” and “priority” are the new Heroes." (2005). Lab 5 Report Extra Credit Warning: This extra credit assignment requires working Lab 5 SLC-3 and also requires some experimentation with SignalTap and is only worth 4 points - so make sure you are completely done with Lab 6 before attempting this assignment - otherwise it is likely not an efficient use of time. Lab 5 report extra credit will require that you use the SignalTap integrated logic analyzer (ILA) to evaluate the performance of your Lab 6 SLC-3 on the FPGA. You will do this by running 3 test programs XOR, Multiplication, and Sort, and generating a trace using SignalTap. As a start, watch the following videos and check out the following tutorial to get familiarized with SignalTap: Signaltap for Verilog Designs Tutorial (with corresponding video from Intel) Video tutorial: SignalTap Video Tutorial Then set up a SignalTap trigger starting at the following points for each test program: PC = 0x1A for XOR test (this starts the capture right after you enter the second value to be XOR'ed) PC = 0x3A for the Multiplier test (this starts the capture right after you enter the second operand) PC = 0x77 for the Sort test, entry into the sort subroutine The goal is to generate a logic analyzer capture of your SLC3 CPU running the 'core algorithm' for each of the above 3 test programs. From that point, you can estimate the actual performance of the SLC3 CPU when running the test programs in lieu of having performance counters on the CPU itself. To this, read test programs and determine when the correct output is first

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