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03/03/2019
Experiment #4
Multiplexers in
Combinational Logic Design
03/03/2019
EEE 3342
Objective:
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The goal of this experiment is to introduce multiplexers in the implementation of
combinational
logic design. In addition, procedural programming in VERILOG will be introduced to the
student.
Apparatus List:
1.
BASYS 3 Board
2. Xilinx
3.
Vivado Tools
4.
Given Function:
F(w,x,y,z)=y'z'w'+y'z+yz'x
Pre-Lab Questions:
1.
Given the Function F (w, x, y, z) generate this function’s truth table. Next, determine
the min-terms (the combination of w, x, y, and z for which
the
output
function
F
is
one).
These combinations determine the input locations of the multiplexer which are
set to one.
The combinations, for which the output is zero, form the input locations of
the multiplexer which are set to zero.
F(w,x,y,z)=y'z'w'+y'z+yz'x
W
X
Y
Z
F(W,X,Y,
Z)
0
0
0
0
1
0
0
0
1
1
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
1
0
1
1
0
1
0
1
1
1
0
1
0
0
0
1
1
0
0
1
1
1
0
1
0
0
1
0
1
1
0
1
1
0
0
0
1
1
0
1
1
1
1
1
0
1
1
1
1
1
0
2.
Draw the logic schematic in your notebook using two 8:1 multiplexers. Consider the
enable input
as
active
high
(Xilinx
has
the
Enable
input
as
active
high
–
E).
03/03/2019
Three
of
the
input variables in the given function F(w,x,y,z) are used as control
inputs to the selection/control 4-2 inputs of each of the 8:1 multiplexers and the fourth
input variable is used to select between the two 8:1 multiplexers using the E input. An
OR gate is used to OR the two 8:1 multiplexer outputs.
3.
Read the rest of this experiment carefully
to
become
familiar
with
it
and
write
down
the Verilog code for the Multiplexer depending on the inputs and outputs.
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Procedures:
1.
Using Xilinx’s Vivado Design Tool and the VERILOG programming language,
design a 16:1 multiplexer.
2.
2. Create VERILOG source file which consists of the code for the multiplexer and
then run the synthesis. Expand the Open Elaborated Design entry under the RTL
Analysis tasks of the Flow Navigator pane and click on Schematic to create the
schematic circuit.
3.
3. After
studying
the
above
VERILOG
programming
examples,
try
to
compile
a
VERILOG programming
module
that
implements
a
16:1
multiplexer
using
procedural
programming. Assign
a
4-bit
bus
S
for
the
select
lines
of
the
multiplexer
and
a
signal
O
for
the
output
(O needs to be
reg type).
4.
4. See Experiment #1&2 on how to design, set the test bench end time and the
simulation end time. Once the simulation is completed, verify if the outputs are in
sync with code.
5.
5. Define a four-bit input BUS S and a single output O. This four-bit bus, S[0],
S[1], S[2] and S[3] should be connected to SW0 (V17), SW1 (V16), SW2(W17),
and SW3(W15) and the O output should be linked to LED0 (LD0) on the BASYS
board by choosing “Package” under schematic. The value of the I/O Std of these
switches should be set to “LVCMOS33”.
6.
6. Generate a .BIT file as explained in Experiment 1 and Implement the design on
the BASYS Board.
By
clicking
on
the
hardware
manager,
and
programming
the
board
with
the implemented design, verify the output on the Board.
-
Figures:
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Figure 1: VERILOG source file for Multiplexer
03/03/2019
Figure 2: RTL Schematic
Figure 3: Scalar Ports
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Figure 5: Simulation Source Code
Figure 6: Waveform Diagram
03/03/2019
Design Specification Plan:
For the experiment, we needed to use four given inputs; W, X, Y, and Z, which resulted
in output F. This output was based on the function: F(w,x,y,z)=y'z'w'+y'z+yz'x For the four
given inputs based off the function they equaled 1, and whatever wasn’t listed was 0 based off a
truth table generated for the function. Knowing where the function needed to equal 1, I used if
statements to generate this. For example, at w’y’z’ I made the statement if (W==0 & Y==0 &
Z==0), F = 1. I repeated these statements with the rest of the function, then finally made an else
statement making F=0 for everything else. I then linked each switch for the initial inputs then
linked LED 0 for F. Finally I synthesized my design and uploaded it onto the board to test it.
Test Plan:
Load the program onto the BASYS 3 Board then begin testing positions for the variables
W, X, Y, and Z corresponding to the truth table. LED Light ON is 1; LED Light off is 0. Switch
OFF is 0; Switch ON is 1.
1.
For the switches the OFF positions represent the primes of the inputs, while the ON
positions represent the normal inputs.
2.
Begin by testing w’x’y’z’, for this part of the function all the switches should be in the
OFF position. This should result in a lit LED.
4.
Test w’x’y’z, then record LED status. If done correctly this should have resulted in a
lit LED.
5.
Test w’xy’z, then record LED status. If done correctly this should have resulted in a lit
LED.
6.
Test w’xyz’, then record LED status. If done correctly this should have resulted in a lit
LED.
7.
Test wx’y’z’, then record LED status. If done correctly this should have resulted in a
lit LED.
8.
Test wx’y’z, then record LED status. If done correctly this should have resulted in a lit
LED.
9.
Test wxy’z, then record LED status. If done correctly this should have resulted in a lit
LED.
10.
Test wxyz’, then record LED status. If done correctly this should have resulted in a lit
LED.
11.
Test other combinations. One should find that the LED is off for any other
combination that is not represented in the function.
Results:
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Since the design was successful, we can use the initial truth table in the Pre-Lab Assignment to
represent our findings.
W
X
Y
Z
F(W,X,Y,
Z)
0
0
0
0
1
0
0
0
1
1
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
1
0
1
1
0
1
0
1
1
1
0
1
0
0
0
1
1
0
0
1
1
1
0
1
0
0
1
0
1
1
0
1
1
0
0
0
1
1
0
1
1
1
1
1
0
1
1
1
1
1
0
Conclusion:
The results proved successful according to the Pre-Lab truth table. There were multiple
ways to do the Verilog source code; however, the easiest in my opinion was to use IF
statements. By using this, all we needed to have was the conditions were the function was 1 and
create an ELSE statement which made any other combination result in 0.
1.
Investigate the function of a lookup table and describe how one works.
The function of a lookup table is that it checks if there is data present before
loading more data into another table, which decreases the runtime of a program.
It then replaces runtime computation with a simpler array indexing operation.
2.
Consider a 16 word by 1 bit lookup table. Give the values stored in each location
0000 binary (word zero) to 1111 binary (word fifteen) for the function F(w, x, y, z).
The truth table that was generated in the pre-laboratory will help here.
W
X
Y
Z
F(W,X,Y,
Decimal
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Z)
Values
0
0
0
0
1
0
0
0
0
1
1
1
0
0
1
0
0
2
0
0
1
1
0
3
0
1
0
0
0
4
0
1
0
1
1
5
0
1
1
0
1
6
0
1
1
1
0
7
1
0
0
0
1
8
1
0
0
1
1
9
1
0
1
0
0
10
1
0
1
1
0
11
1
1
0
0
0
12
1
1
0
1
1
13
1
1
1
0
1
14
1
1
1
1
0
15
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