lab03

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Electrical Engineering

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Dec 6, 2023

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Lab 03 CPSC 121, 2023W1 Monday Sections: Tuesday Sections: Wednesday Sections: Thursday Sections: Friday Sections: October 16, 2023 October 03, 2023 October 04, 2023 October 05, 2023 October 06, 2023

Important Information (no marks) Pre-labs must be submitted on Gradescope by 9 AM on the day of your lab session. Labs must be completed during the session, not beforehand. Pre-labs are to be completed and submitted individually. You may discuss general ideas partners but you may not work together on the same pre-lab. You must assign the correct pages to each question on Gradescope. We will not grade any answer that isn’t properly assigned. This video has information about how to submit assignments on Gradescope. Each lab is comprised of numbered TODOs. Raise your hand for TA’s to check off each TODO as you complete them. You should continue to work on the rest of the lab while waiting, or you will run out of time. The labs in CPSC 121 have a standard marking scheme. Your lowest lab grade is dropped. There are no make-up labs. All labs are worth 10 marks. — 2 marks for correctly doing the pre-lab. — 5 marks for TODO: in red bold. (completion mark). — 1 mark for TODO (Further Analysis): (discussion with TA). — 1 mark for lab survey (done individually). — 1 mark for clean-up for labs that use the Magic Box, otherwise another TODO. 1 bonus mark can be earned at the TA’s discretion for completing the Challenge Question, which can carry over to your overall course mark. Labs end 10 minutes before the next hour. Students are expected to complete the lab and clean up in 1 hour and 50 minutes. Do not expect TODOs to be checked off during the spare 10 minutes, it will be at the TA’s discretion. You will not be allowed to complete a lab if you are more than 7 minutes late.

Working with Multiplexers (1 mark) . Look up the LS157 chip in The Magic Box User’s Manual (you can find it in at the Handouts Module on Canvas or here). The L.S157 chip contains four 1-of-2 multiplexers (with a single shared select input). Be sure that you read the documentation on the ENABLE input carefully! FYIoNETN Y R YD 5 § N AT s FIOME Y O3t YWoyre uimy oo oyrauniimn LAASN fy ANt PoASIY O YA Subcircuits (1 mark) . Circuit design is done much like software design. In code, we break our programs up into functions or methods: these can then act as self- contained modules, which can be reused easily. This modularity is also a principle of good circuit design. Download the file priority.circ on Canvas (go to the Labs page on Canvas and search for Lab 3 files), and open it in Logisim (File, then Open)(Note: Students using MacOS may need to move priority.circ to their home folder or desktop). Modules in Logisim are represented by rectangles. You will see a program that has six identical modules wired up in a chain:

® file Edit Project Simulate FPGA Window Help main of priority - Logisim-evolution v3.7.2 - O Design Simulate 4RJA DD » +0r+@x =] priority umait\ e yEfph o i o B re e e e e e O P P P P P P * W Input/Output Properties State b b b b o b Circuit: main FPGA supported Circuit Name main Shared Label Shared Label Fa.. —~ East Shared Label F.. SansSerif Plain Appearance Classic Logisim Use fixed box-si_No . Our goal with this activity is to edit the P module to implement what is called a priority chain. In this priority chain, the only light that will be turned on is the one at the leftmost module where b is on. All other lights remain turned off. This module of the chain is said to have the priority. We also say that stages to the left have higher priority than stages to the right. Here is an example: “ . We see in this image that the first module where b = TRUE has x illuminated, but later modules with b on do not. Also, note that the first a of the circuit is connected to ground (FALSE). Therefore, we want a circuit which has the properties: 4

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