Prelab4_FET amplifier frequency response (rev)

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Dec 6, 2023

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1 | P a g e University of Massachusetts Department of Electrical and Computer Engineering ECE 310 Circuits and Electronics II Fall 2023 Prelab 4 NMOS Amplifier with bandwidth limitation In this prelab, you will design an NMOS amplifier that satisfies certain gain and bandwidth requirements when driving a specified capacitive load. You will need to pick the resistors for the circuit and choose bias current (I D ). You will need to hand-calculate small signal gain, bandwidth, and input impedance. You will simulate the circuit and compare the simulated results to your hand calculations. In the lab you will construct the amplifier and measure its gain and bandwidth properties. Using the topology in Figure 1, the amplifier must meet the following specifications: 1. have a small signal voltage gain |A mid | > (see Table 1) at midband f mid = 200Hz. 2. be capable of delivering to load C L an undistorted peak-to-peak output voltage a. of at least maxV out (f mid ) (see Table 1) at midband and b. of at least maxV out (f x ) (see Table 1) at frequency f x . 3. have a small signal input resistance (R i ) > 35 k W at midband 4. use less power than P max (see Table 1) 5. use +5V DC supply 6. use the NMOS FETs in the HCF4007 MOS array. To model the NMOS device, use K n = 1.0 mA/V 2 , V TN = 1.4V. These values were found to work reasonably well to fit data measured on the devices in HCF4007 chips. Figure 1 Single stage NMOS amplifier with capacitive load Q 1 V DD V out v in C L R 1 R 2 R d C 1 1uF

2 | P a g e Design Specifications The design specifications for this amplifier are assigned according to the last digit in your student ID number. On your prelab, write your student ID and the corresponding specifications from the table below. Notes: C L is the load capacitance in nanofarads. At f x the load capacitance is drawing current and thus loading the amplifier. You must make your design such that this loading does not distort a signal having an output amplitude as big as “maxV out (f x )” in peak-to-peak volts. At low frequencies the capacitor no longer loads the amplifier, and the output signal can be bigger. You must make your design such that a signal with output amplitude as big as “maxV out (f mid )” is not distorted. Your amplifier can use no more than P max DC power. Your amplifier must have a gain of at least A mid = V out /V in at low frequencies and small signals . I.D. ends with: 0 or 1 2 or 3 4 or 5 6 or 7 8 or 9 C L 10 nF 10 nF 4.7 nF 4.7 nF 2 nF f x 2 KHz 4 KHz 4KHz 7KHz 20KHz maxV out (f x ) 1.5Vpp 1.0Vpp 2.4 Vpp 2.2Vpp 2Vpp maxV out (f mid ) 2Vpp 1.2Vpp 3 Vpp 2.8Vpp 2.8Vpp P max 1.7mW 2mW 2mW 3.5mW 3.75mW Small signal A mid 5V/V 4.5V/V 4.5V/V 3.25V/V 2.5 V/V Table 1. Amplifier specifications assigned according to student I.D. number.

3 | P a g e Design Procedure You first need to choose the DC I D to be at least a 3 or 4 times larger than the peak AC current (Specification 2b). You can estimate the peak AC current by calculating the peak current going through the load capacitor at the largest specified frequency when the amplifier is driven at the largest voltage for that frequency. Next choose a desirable DC drain voltage, V D . In order to satisfy specification 2 (Specification 2a) you need to choose V D so that the total drain voltage (AC plus DC) will at all times be below V DD but large enough that Q1 stays in saturation. This will keep clipping and distortion from happening. The largest voltage swing will occur at midband frequency. You will find that there is a range of V D choices that will satisfy specification 2b Once you have selected I D and V D , you can calculate a possible R D . Adjust V D and I D as necessary to find a resistor value that is available in the lab. Now you have what you need to check the gain. Calculate the expression (in terms of g m , R d , C L , etc. ) for the transfer function relating the small signal phasor quantities V out and V in . You can assume C 1 = infinity. For a first design, assume R 1 and R 2 are infinity as well. From your transfer function, find the mid-band gain and be sure it meets the specifications (Specification 1). If not, you can adjust parameters like g m and R D until you get enough gain and then adjust the corresponding values of I D and V D . Remember that small signal parameters like g m are coupled to I D , and you cannot change one without readjusting the other 1 . Calculate the f -3dB for your design; you will compare the result to simulation and measurement. Then find R 1 and R 2 . To do this, first find the value of V GS that corresponds to the drain current you chose. V GS and V D are related to each other by the voltage divider expression, and since you now have targets for the voltages, you can determine the necessary ratio of R 1 / R 2 . You can choose any values in the parts list that will give you this ratio…….except that you need to consider the input resistance(Specification 3)) Find the small signal expression for the input 1 g m = K(V GS – V TN ) = (2KI D ) 1/2

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4 | P a g e resistance seen by the v in source at midband frequencies. (Be careful with this. If your expression does not have a g m in it, you have a mistake.) Pick R 1 , R 2 big enough to satisfy the input resistance specification. Do not make them any bigger than necessary since your circuit will be more sensitive to noise. Now recalculate your gain and bandwidth including R 1 , R 2 and confirm that all the specifications 1-4 are still met. (0) Be sure your homework solution has your student I.D. and the list of amplifier specifications you are targeting. (1) Turn in no more than three pages, showing clearly how you arrived at your final design. Include a schematic showing your hand calculated DC voltages and currents. (You can enter these on your CircuitLab schematic if convenient.) (2) a) Turn in your initial hand calculation of transfer function, mid-band gain, bandwidth 2 , and midband input resistance. b) Turn in your re-calculation your gain and bandwidth including R 1 , R 2 and confirm that all the specifications 1-4 are still met. Simulation Now check your design by simulating it with CircuitLab (or PSPICE; see Appendix I.) Set up the FET model in the simulator using the parameters in item #6 above. Use the DC simulator in CircuitLab. The very first thing to check is whether the DC levels in your simulation match up with your hand calculations. If your hand calculations do not agree with your simulation results, you need to find out why. In this project, agreement to 15% is satisfactory. Compare the simulated DC power dissipation to your calculation. 2 Assume the “bandwidth” of this circuit is f -3dB .

5 | P a g e The gain specification and bandwidth calculation involve small-signal quantities. The simulator uses a linear analysis tool to efficiently analyze small signal relationships. Your simulation should be set for Frequency Domain simulation, and your schematic should include sine source. You should plot magnitude in dB 3 versus frequency on a log scale. Mark on the plot the midband gain and f -3dB (the high frequency cut-off). Compare simulated midband gain to your hand calculated gain (15% is about 0.6 dB.) Compare the simulated f -3dB to calculation. To check that your design will drive the capacitive load to the required peak-to-peak specification, you will need to do a large signal simulation. For this you will need to use a time domain simulation and plot the required voltages versus time. First use a small amplitude input signal at f mid and observe the peak output voltage. Calculate the gain and check that your time domain simulation is producing the same gain as the small signal AC frequency domain simulation produced. Then increase the size of the input until the output sinusoid shows a peak to peak value that matches Specification 2. The output should be a pure sinusoid with no clipping. Plot both the input voltage and the output voltage on the same set of axes. Use a small enough value for the “time step” so your simulator plots are smooth. (3) Turn in your simulator schematic, and show the DC voltages on all nodes. Create a table to compare simulated V D , V G and I D to your hand calculations. Note the % error. If you have more than 15% error you need to find out why. (4) Turn in a simulator plot of |A V | in dB versus log frequency. Note on the plot the midband gain and the f -3dB ; Create a table to compare these to your hand calculations. Note the % error. If you have more than 15% error you need to find out why. (5) Turn in a simulator plots of v o and v i versus time on the same set of axes showing that you meet the specifications for gain and maximum peak to peak output voltage. Turn in two plots, 3 Most linear simulators plot V out in dBV, which is 20log(V out ) with the input set to 1V. It does not matter what the schematic says the input amplitude is. The input voltage does matter for the time domain simulator .

6 | P a g e one for the midband frequency and one for the high frequency in Specification 2 . The output should exhibit no distortion in both cases. Make sure that you choose a display format such that both v o and v i are easily visible!

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7 | P a g e Appendix I. Notes for setting up the device models using the schematic capture version of PSPICE Save the '.sched' program (with your name in the title!) Use Get new part under the DRAW menu Choose the "Break-out" library Choose "MbreakN" as your device model and place it on the schematic Click on the nMOS FET (it now looks red) Choose MODEL under the EDIT menu Go to the lowest of the options, "Choose Instance Model" You can now specify your own values of the parameters for the nMOS device, they can be typed in the same format as you would in the netlist: Create this line: .model MbreakN-X NMOS ( kp=600u Vto=1.3V L=10u W=10u lambda=0.04) Save this model 4 . The numbers in the above line are just examples. You should use the ones in the text. Plotting in PSPICE: To get log scale in frequency, edit the simulation settings for AC sweep/noise such that the sweep type is set to logarithm/decade. To get the output voltage plotted in db go to the menu bar: PSpice/Markers/Advanced/dB Magnitude of Voltage, and then put the VDB marker on the output node. 4 The model argument kp stands for k’. Recall that K = k’*W/L