prelim1-19fa

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Jan 9, 2024

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Fall 2019 CS 3410 Prelim 1 Please turn off and stow away all electronic devices. You may not use them for any reason during the exam. Do not bring them with you if you leave the room temporarily. This is a closed book and notes examination. You may use the 3-sided reference sheet at the back of the exam. You may use the 4th side as scratch paper. There are 8 problems . Make sure you have the whole exam. You have 90 minutes to complete 90 points. Use your time accordingly. Question Points Score 1 4 2 7 3 9 4 16 5 20 6 10 7 12 8 12 Total: 90 It is a violation of the Academic Integrity Code to look at any exam other than your own, to look at any other reference material, or to otherwise give or receive unauthorized help. We also ask that you not discuss the exam with anyone who has not yet taken it. Academic Integrity is expected of all students of Cornell University at all times, whether in the presence or absence of members of the faculty. Understanding this, I declare I shall not give, use or receive unauthorized aid in this examination. Signature: Date Name: NetID
1. [4 points] A rolling stone gathers no CMOS. Recall that a p-transistor connects source to drain when a negative/zero charge is applied to the gate. What function does the following CMOS diagram implement? Your Answer: ground V supply A B C OUT D E A B ground C ground E D 2. 01 is the lonelist number. (a) [2 points] Express the unsigned binary number 100100101 in unsigned octal (base 8). Your Answer: (b) [2 points] Express the 2s complement number 100100101 in decimal (base 10). Your Answer: (c) [3 points] Fractional Binary Encoding is a binary encoding with a decimal point. The columns to the right of the decimal point continue in the pattern of decreasing powers of 2: the column immediately to the right of the point is the 2 - 1 ( = 1 / 2) column, next to that is the 2 - 2 ( = 1 / 4) column, and so on. Given your understanding of two’s complement, what is the value of the 6-bit two’s complement fractional binary number 101.010 ? Your answer must be expressed as a single number. Your Answer: Page 2
3. [9 points] Universal Gatecare? A NAND gate is called a universal gate because you can build all other logic gates using only NAND gates. Each circuit below is a logical gate built exclusively out of NAND gates. What is the gate functionality of each circuit? Your Choices are: A. NOT B. AND C. NAND D. OR E. NOR F. XOR G. XNOR H. None of these Note: many circuits show a single input ( a or b ) sent to both inputs of the same NAND gate. a b Q Your Answer: a Q Your Answer: a b Q Your Answer: Page 3
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4. Sign of the Times Adds . Recall that the leftmost bit of a sign magnitude number indicates positive (0) or negative (1). Recall also that sign magnitude addition requires some unique manipulations. Your task is to perform these manipulations. Given two 5-bit sign magnitude numbers, X and Y, add them together, using an AddSub subcircuit (that calculates A + B when op=0 , and A - B when op=1 ). You may use standard 2-input logic gates, muxes, and a comparator (shown on the first page of the reference sheet). Approach: If the signs of the two inputs match, add the inputs as unsigned numbers. If they differ, subtract the smaller magnitude from the larger; keep the sign of the larger. Do not worry about overflow or the B input. (a) [4 points] Draw a circuit that assigns (1) op to the AddSub subcircuit. X Y 5 5 X[4] Y[3-0] Y[4] X[3-0] op 1 skip skip Z[4] skip AddSub Z[3-0] 4 A 4 B Page 4
Copied from previous page for your convenience: Approach: If the signs of the two inputs match, add the inputs as unsigned numbers. If they differ, subtract the smaller magnitude from the larger; keep the sign of the larger. Do not worry about overflow or the B input. (b) [6 points] Draw a circuit that assigns (2) the A input to the AddSub subcircuit. X Y 5 5 X[4] Y[3-0] Y[4] X[3-0] 2 skip op skip Z[4] skip AddSub Z[3-0] 4 A 4 B Page 5
Copied from previous page for your convenience: Approach: If the signs of the two inputs match, add the inputs as unsigned numbers. If they differ, subtract the smaller magnitude from the larger; keep the sign of the larger. Do not worry about overflow or the B input. (c) [6 points] Draw a circuit that assigns (3) Z[4], the output sign bit. X Y 5 5 X[4] Y[3-0] Y[4] X[3-0] Z[4] 3 skip op skip AddSub Z[3-0] 4 A 4 B skip Page 6
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5. C and Assembly (a) [12 points] What is printed when this program runs? 3 int tmp; 4 5 int set1( int val, int *vptr) { 6 *vptr = val + 6; 7 val++; 8 printf( "1: val = %d\n" , val); 9 printf( "2: *vptr = %d\n" , *vptr); 10 return (tmp + *vptr + val); 11 } 12 13 void set2( int val, int *vptr) { 14 *vptr = val + 3; 15 printf( "3: val = %d\n" , val); 16 printf( "4: *vptr = %d\n" , *vptr); 17 printf( "5: tmp = %d\n" , tmp); 18 } 19 20 int main() { 21 int val = 5; 22 int *vptr = &val; 23 tmp = *vptr; 24 set2(set1(val, vptr), vptr); 25 printf( "6: val = %d\n" , val); 26 } 1: val = 2: *vptr = 3: val = 4: *vptr = 5: tmp = 6: val = (b) [8 points] Convert the following C code into RISC-V assembly, using the instructions and pseudo-instructions on your reference sheet. You are welcome to use labels. Assume that the compiler placed x in x20 and y in x21 . The only register convention you must uphold is that x0 is the zero register. Use all other registers ( x1-x31 ) as you like. if (x > y) y += (x-y)*2; else x--; Page 7
6. Know your limits. Different processor designs are more or less sensitive to certain innovations or constraints. Show how the innovations/constraints below affect the following processor designs: Your Choices are: A. a single-cycle processor B. a multi-cycle processor C. a 5-stage pipelined processor, branches resolved at stage 3 D. a 15-stage pipelined processor, branches resoled at stage 7 E. None Performance is defined as the time it takes to execute a given workload, and this workload re- mains the same. Assume that, when necessary, a processor design will be modified to guarantee correct execution of the workload without the given innovation. Innovation: inverting the clock on the register file so that it performs writes during the first half of the clock cycle (a) [2 points] Which processor design(s) make use of this innovation? Select all that apply: A B C D E Innovation: branch prediction (b) [2 points] Which processor design(s) will have the exact same performance with and with- out a branch predictor? Select all that apply: A B C D E (c) [2 points] Which processor design(s) will experience the biggest performance hit when the branch predictor is turned off? Select all that apply: A B C D E Innovation: a fast clock (d) [2 points] Which processor design(s) will have the exact same performance even if the clock period doubles? Select all that apply: A B C D E Constraint: a register tax. Suppose you will be charged extra manufacturing cost for each register (D Flip Flop) you use. (e) [2 points] Which processor design(s) will experience the least (but > 0 ), absolute manu- facturing cost increase with the introduction of a register tax? Select all that apply: A B C D E Page 8
7. That’s very forward of you. Consider a 5-stage pipelined processor that reads from the register file during the first half of the cycle and writes to the register file during the second half of the cycle. Below we propose 3 new bypasses for the pipeline. For parts (a) and (b), state whether the bypass is useful. If not , explain why. If it is useful , provide a sequence of instructions that takes advantage of the bypass. Circle the producing and consuming register name in the instructions to show source and destination of the communication. If the sequence is not back-to-back, include the correct number of nop instructions between them. For example: addi x0 , x0 , 0 nop addi x0 , x0 ,0 (a) [4 points] Is bypass #1 useful? Yes No If no, explain why. If yes, give an instruction sequence example. (b) [4 points] Is bypass #2 useful? Yes No If no, explain why. If yes, give an instruction sequence example. (c) [4 points] Your friend tells you that bypass #3 solves the load-use stall problem. Does it? A. No, never B. Yes, always C. Yes, sometimes D. Yes, but at the cost of a slower clock Your answer: Explain. Page 9
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8. [12 points] The road less Taken . The transition diagram below depicts a Moore Machine expressing the behavior of a 2-bit saturating counter used for branch prediction. The output tells the processor whether a branch should be predicted taken (1) or not (0). The input is the actual branch result (taken (1) or not taken(0)) calculated at execute. N 0 n 0 t 1 T 1 0 0 0 1 1 1 0 1 start States should be encoded as follows: State S 1 S 0 N 00 n 01 t 10 T 11 Draw the circuit showing the combinational logic for the output and S 1 ’ (the next state logic for the more significant state bit, S 1 ). You can use logic gates with any number of inputs, but circuits with fewer and simpler gates will receive more points. This is achievable by quick inspection as shown in class. D Q C A ctual (Input) S 0 S 1 Prediction (Output) clk D Q C S 1 skip Page 10